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PDF 25VF512 Data sheet ( Hoja de datos )
| Número de pieza | 25VF512 | |
| Descripción | SST25VF512 | |
| Fabricantes | Silicon Storage Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 25VF512 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
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A Microchip Technology Company
512 Kbit SPI Serial Flash
SST25VF512
Data Sheet
SST serial flash family features a four-wire, SPI-compatible interface that allows
for a low pin-count package occupying less board space and ultimately lowering
total system costs. SST25VF512 SPI serial flash memory is manufactured with
SST's proprietary, high-performance CMOS SuperFlash technology. The split-
gate cell design and thick-oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
Features
• Single 2.7-3.6V Read and Write Operations
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• 20 MHz Max Clock Frequency
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over Byte-Pro-
gram operations
• End-of-Write Detection
– Software Status
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the status
register
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Packages Available
– 8-lead SOIC (4.9mm x 6mm)
– 8-contact WSON
• All non-Pb (lead-free) devices are RoHS compliant
©2011 Silicon Storage Technology, Inc.
www.microchip.com
DS25076A
10/11
1 page  
A Microchip Technology Company
512 Kbit SPI Serial Flash
SST25VF512
Memory Organization
Data Sheet
The SST25VF512 SuperFlash memory array is organized in 4 KByte sectors with 32 KByte overlay
blocks.
Device Operation
The SST25VF512 is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF512 supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
MODE 3
SCK MODE 0
MODE 3
MODE 0
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON T CARE
MSB
HIGH IMPEDANCE
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1192 F34.6
Figure 2: SPI Protocol
©2011 Silicon Storage Technology, Inc.
5
DS25076A
10/11
5 Page 
A Microchip Technology Company
512 Kbit SPI Serial Flash
SST25VF512
Data Sheet
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status register or wait TBP for the completion of
the internal self-timed Byte-Program operation. See Figure 5 for the Byte-Program sequence.
CE#
MODE 3
SCK MODE 0
0 1 2345 6 78
15 16
23 24 31 32 39
SI 02
MSB
SO
Figure 5: Byte-Program Sequence
ADD.
MSB
ADD.
HIGH IMPEDANCE
ADD. DIN
MSB LSB
1192 F08.11
©2011 Silicon Storage Technology, Inc.
11
DS25076A
10/11
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet 25VF512.PDF ] | |
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