Datasheet.kr   

25VF512 PDF 데이터시트 ( Data , Function )

부품번호 25VF512 기능
기능 SST25VF512
제조업체 Silicon Storage Technology
로고 Silicon Storage Technology 로고 


이 페이지 하단에 미리보기 및 25VF512 다운로드 (pdf 파일) 링크가 있습니다.




전체 29 페이지

No Preview Available !

25VF512 데이터시트, 핀배열, 회로
A Microchip Technology Company
512 Kbit SPI Serial Flash
SST25VF512
Data Sheet
SST serial flash family features a four-wire, SPI-compatible interface that allows
for a low pin-count package occupying less board space and ultimately lowering
total system costs. SST25VF512 SPI serial flash memory is manufactured with
SST's proprietary, high-performance CMOS SuperFlash technology. The split-
gate cell design and thick-oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
Features
• Single 2.7-3.6V Read and Write Operations
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• 20 MHz Max Clock Frequency
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over Byte-Pro-
gram operations
• End-of-Write Detection
– Software Status
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the status
register
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Packages Available
– 8-lead SOIC (4.9mm x 6mm)
– 8-contact WSON
• All non-Pb (lead-free) devices are RoHS compliant
©2011 Silicon Storage Technology, Inc.
www.microchip.com
DS25076A
10/11




25VF512 pdf, 반도체, 판매, 대치품
A Microchip Technology Company
Pin Description
512 Kbit SPI Serial Flash
SST25VF512
Data Sheet
CE#
SO
WP#
VSS
18
27
Top View
36
45
1192 08-soic P1.4
8-lead SOIC
VDD
HOLD#
SCK
SI
CE# 1
SO 2
WP# 3
Top View
8 VDD
7 HOLD#
6 SCK
VSS 4
5 SI
1192 08-wson P1a.6
8-contact WSON
Figure 1: Pin Assignments
Table 1: Pin Description
Symbol Pin Name Functions
SCK
Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI Serial Data To transfer commands, addresses, or data serially into the device.
Input
Inputs are latched on the rising edge of the serial clock.
SO Serial Data To transfer data serially out of the device.
Output
Data is shifted out on the falling edge of the serial clock.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold
To temporarily stop serial communication with SPI flash memory without resetting the
device.
VDD Power Sup- To provide power supply (2.7-3.6V).
ply
VSS Ground
T1.7 25076
©2011 Silicon Storage Technology, Inc.
4
DS25076A
10/11

4페이지










25VF512 전자부품, 판매, 대치품
A Microchip Technology Company
512 Kbit SPI Serial Flash
SST25VF512
Data Sheet
Status Register
The software status register provides status on whether the flash memory array is available for any
Read or Write operation, whether the device is Write enabled, and the state of the memory Write pro-
tection. During an internal Erase or Program operation, the status register may be read only to deter-
mine the completion of an operation in progress. Table 4 describes the function of each bit in the
software status register.
Busy
The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for
the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is
ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the
Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset),
it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase)
commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming reached its highest memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Block Protection (BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 3, to be
software protected against any memory Write (Program or Erase) operations. The Write-Status-Regis-
ter (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-
Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are both 0. After
power-up, BP1 and BP0 are set to 1.
©2011 Silicon Storage Technology, Inc.
7
DS25076A
10/11

7페이지


구       성총 29 페이지
다운로드[ 25VF512.PDF 데이터시트 ]


 
구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

상호 : 아이지 인터내셔날

사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ]


 

관련 데이터시트

부품번호상세설명 및 기능제조사
25VF512

SST25VF512

Silicon Storage Technology
Silicon Storage Technology

DataSheet.kr    |   2020   |  연락처   |  링크모음   |   검색  |   사이트맵