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IRFZ48S 데이터시트 PDF




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부품번호 IRFZ48S 기능
기능 Power MOSFET ( Transistor )
제조업체 Vishay
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IRFZ48S 데이터시트, 핀배열, 회로
www.vishay.com
IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
Qg (Max.) (nC)
Qgs (nC)
Qgd (nC)
Configuration
60
VGS = 10 V
110
29
36
Single
0.018
D
I2PAK (TO-262)
D2PAK (TO-263)
FEATURES
• Advanced process technology
• Surface mount (IRFZ48S, SiHFZ48S)
• Low-profile through-hole (IRFZ48L, SiHFZ48L)
• 175 °C operating temperature
Available
• Fast switching
• Material categorization: for definitions of
compliance
please
see
www.vishay.com/doc?99912
Available
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.
G
DS
G
D
S
G
S
N-Channel MOSFET
DESCRIPTION
Third generation power MOSFETs from Vishay utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
Power MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in a
wide variety of applications.
The D2PAK is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D2PAK is suitable for high current applications because of
its low internal connection resistance and can dissipate up
to 2 W in a typical surface mount application.
The through-hole version (IRFZ48L, SiHFZ48L) is available
for low-profile applications.
ORDERING INFORMATION
Package
Lead (Pb)-free and halogen-free
Lead (Pb)-free
Note
a. See device orientation.
D2PAK (TO-263)
SiHFZ48S-GE3
IRFZ48SPbF
I2PAK (TO-262)
SiHFZ48L-GE3
-
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
Continuous Drain Current f
Pulsed Drain Current a, e
VGS at 10 V
TC = 25 °C
TC = 100 °C
ID
IDM
Linear Derating Factor
Single Pulse Avalanche Energy b, e
EAS
Maximum Power Dissipation
Peak Diode Recovery dV/dt c, e
TC = 25 °C
TA = 25 °C
PD
dV/dt
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak temperature) d
for 10 s
TJ, Tstg
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, Starting TJ = 25 °C, L = 22 μH, Rg = 25 , IAS = 72 A (see fig. 12).
c. ISD 72 A, dI/dt 200 A/μs, VDD VDS, TJ 175 °C.
d. 1.6 mm from case.
e. Uses IRFZ48, SiHFZ48 data and test conditions.
f. Calculated continuous current based on maximum allowable junction temperature.
LIMIT
60
± 20
50
50
290
1.3
100
190
3.7
4.5
-55 to +175
300
UNIT
V
A
W/°C
mJ
W
V/ns
°C
S15-1659-Rev. D, 20-Jul-15
1
Document Number: 90377
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000




IRFZ48S pdf, 반도체, 판매, 대치품
www.vishay.com
IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
S15-1659-Rev. D, 20-Jul-15
4
Document Number: 90377
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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IRFZ48S 전자부품, 판매, 대치품
www.vishay.com
IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L
Vishay Siliconix
D.U.T.
+
-
Peak Diode Recovery dV/dt Test Circuit
+ Circuit layout considerations
Low stray inductance
Ground plane
Low leakage inductance
current transformer
-
-+
Rg
dV/dt controlled by Rg
+
Driver same type as D.U.T.
ISD controlled by duty factor “D”
- VDD
D.U.T. - device under test
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Body diode forward drop
Inductor current
VDD
Ripple 5 %
Note
a. VGS = 5 V for logic level devices
ISD
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?90377.
S15-1659-Rev. D, 20-Jul-15
7
Document Number: 90377
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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