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PDF 11NK100Z Data sheet ( Hoja de datos )
| Número de pieza | 11NK100Z | |
| Descripción | STW11NK100Z | |
| Fabricantes | STMicroelectronics | |
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STW11NK100Z
STW11NK100Z
N-channel 1000V - 1.1Ω - 8.3A - TO-247
Zener - Protected SuperMESH™ PowerMOSFET
General features
Type
VDSS
(@Tjmax)
RDS(on)
ID
Pw
STW11NK100Z 1000 V < 1.38 Ω 8.3 A 230W
■ Extremely high dv/dt capability
■ 100% avalanche tested
■ Gate charge minimized
■ Very low intrinsic capacitances
■ Very good manufacturing repeatibility
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage MOSFETs including revolutionary
MDmesh™ products.
Applications
■ Switching application
TO-247
Internal schematic diagram
Order codes
Part number
STW11NK100Z
Marking
W11NK100Z
Package
TO-247
Packaging
Tube
July 2006
Rev 2
1/14
www.st.com
14
1 page  
STW11NK100Z
2 Electrical characteristics
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown
voltage
ID = 1mA, VGS= 0
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = Max rating,
VDS = Max rating,
Tc = 125°C
IGSS
VGS(th)
RDS(on)
Gate body leakage current
(VGS = 0)
VGS = ± 20V
Gate threshold voltage
VDS = VGS, ID = 100µA
Static drain-source on
resistance
VGS = 10V, ID = 4.15 A
Min. Typ. Max. Unit
1000
V
1 µA
50 µA
±10 µA
3 3.75 4.5 V
1.1 1.38 Ω
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs (1)
Ciss
Coss
Crss
Forward transconductance VDS =15V, ID = 4.15A
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =25V, f=1 MHz, VGS=0
9
3500
270
60
S
pF
pF
pF
Cosseq(2).
Equivalent output
capacitance
VGS=0, VDS =0V to 500V
170
pF
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Off-voltage rise time
Fall time
VDD=800 V, ID= 8A,
RG=4.7Ω, VGS=10V
(see Figure 16)
27 ns
18 ns
98 ns
55 ns
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD=800V, ID = 8A
VGS =10V
113 162 nC
18 nC
60 nC
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
5/14
5 Page 
STW11NK100Z
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/14
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