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PDF MC68160AFB Data sheet ( Hoja de datos )
| Número de pieza | MC68160AFB | |
| Descripción | ENHANCED ETHERNET TRANSCEIVER | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Freescale Semiconductor, Inc.Order this document by MC68160A/D
Enhanced Ethernet Transceiver
MC68160A
The MC68160A Enhanced Ethernet Interface Circuit is a BiCMOS device
which supports both IEEE 802.3 Access Unit Interface (AUI) and 10BASE–T
Twisted Pair (TP) Interface media connections through external isolation
transformers. It encodes NRZ data to Manchester data and supplies the
signals which are required for data communication via 10BASE–T or AUI
interfaces. The MC68160A gluelessly interface to the Ethernet controller
contained in the MC68360 Quad Integrated Communications Controller
(QUICC) device. The MC68160A also interfaces easily to most other
industry–standard IEEE 802.3 LAN controllers. Prior to twisted pair data
reception, Smart Squelch circuitry qualifies input signals for correct
amplitude, pulse width, and sequence requirements.
• Automatic Twisted Pair Wiring Polarity Fault Detection and Correction
Option
• Automatic Port Selection Option with Status Output
• Driver Pre–emphasis for Twisted Pair Output Data
• Crystal Controlled Clock Oscillator or External Clock Generator Option
• Digital Phase–Locked–Loop (DPLL) Timing Recovery and Data Decoding
• Standby Mode with Reduced Power Consumption
• Twisted Pair Signal Quality Error (Heartbeat) Test Option
• Diagnostic Local Loop Back Option
• Transmit, Receive and Collision Detection Status Output
• Full–Duplex Operation Option on Twisted Pair Port
• Twisted Pair Jabber Detection and Status Output
• Link Integrity Testing and Status Output
The sale and use of this product is licensed under technology covered by one
or more Digital Equipment Corporation patents.
ENHANCED ETHERNET
INTERFACE TRANSCEIVER
SEMICONDUCTOR
TECHNICAL DATA
52 1
FB SUFFIX
PLASTIC PACKAGE
CASE 848D
(LQFP–52)
ORDERING INFORMATION
Device
Operating
Temperature Range Package
MC68160AFB
TA = 0° to + 70°C
LQFP
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Rev 1
1 page  
Freescale SMeCm68i1c6o0nAductor, Inc.
Table 1. Pin Function Description (continued)
Pin(s)
Symbol
Type
Name/Function
OSCILLATOR AND FREQUENCY MULTIPLIER
12 MFILT
C Frequency Multiplier Filter Connection Point: An external resistor capacitor filter must be
attached to this pin.
16 X1 I/C Oscillator Inverter Input and Crystal Connection Point: When connected for crystal
CMOS oscillator operation, the frequency of the clock which appears at TCLK is half that of the
crystal oscillator. As an option, instead of connecting to a crystal, X1 may be driven from an
external 20 MHz CMOS compatible clock generator.
17 X2 O/C Oscillator Inverter Output and Crystal Connection Point: This pin is used only for the
CMOS connection of an external crystal and capacitor. It must be left unconnected if X1 is driven by
an external CMOS Clock generator.
MODE SELECT
3 CS0
4 CS1
5 CS2
6 LOOP
9 APORT
27 TPSQEL
28 TPFULDL
29 TPAPCE
46 TPEN
I Mode Select: The logic states applied to these pins select the appropriate interface for the
TTL desired IEEE–802.3 controller or enable the standby mode. When the standby mode is
selected, the MC68160A power supply current is greatly reduced. Additionally, in the standby
mode, all of the controller inputs and outputs are driven to the high impedance state.
I Diagnostic Loopback: Asserting this function causes serial NRZ data at the TX input to be
TTL Manchester encoded and then looped back through the Manchester decoder, appearing at
the RX output. This diagnostic loopback function operates independent of Twisted Pair (TP)
or Access Unit Interface (AUI) port connectivity or activity. Neither the TP port nor the AUI
port transmits data from the controller while diagnostic loopback is selected. Likewise, the
controller interface receives data neither from the TP nor the AUI receivers while in this
mode. The polarity fault detection and link integrity functions are not inhibited by the
diagnostic loopback mode. If otherwise enabled, they continue to function. If the twisted pair
port is selected, and TPSQEL is driven to the low logic state, a collision detect pulse is
delivered following each transmission to simulate the twisted pair SQE test.
I Automatic Port Selection Enable: When high, MC68160A will automatically select the TP
TTL or AUI port based on the presence or absence of valid link beats or frames at the TP receive
input. If the AUI port is automatically selected, the MC68160A will continue to produce link
pulses for the TP port. Changing ports requires approximately 1.0 ms to allow the circuitry for
the new port to resume normal operation. The power consumption is minimized in the
circuitry associated with the unselected port.
I Twisted Pair Signal Quality Error Test Enable: Forcing this pin low enables testing of the
TTL internal TP collision detect circuitry after each transmit operation to the TP media. This
function provides a simulated collision to as much of the MC68160A collision detect circuitry
as possible without affecting the attached twisted pair channel. A normal SQE test results in
a high logic state at the CLSN controller interface pin which begins 6 to 16–bit times after the
last transition of a transmitted signal and continues for 5 to 15–bit times. (When the AUI port
is selected, SQE test signals are generated by the coaxial cable transceiver and delivered to
the controller via the MC68160A ACX+/– receive inputs)
I Twisted Pair Full Duplex Mode Select: Forcing this pin low allows simultaneous transmit
TTL and receive operation on the twisted pair port without an indicated collision. This pin is not to
be asserted with LOOP as a test mode is enabled that disrupts normal operation.
I Twisted Pair Automatic Polarity Correction Enable: When TPAPCE is high, automatic
TTL polarity correction is enabled, and MC68160A will internally correct for a polarity fault on the
receive circuit. Additionally, when TPAPCE is high, the presence of a polarity fault is
indicated on TPPLR.
I/O Twisted Pair Port Enable: If APORT is low, TPEN is an input which determines whether the
TTL AUI port (TPEN low) or TP port (TPEN high) will be manually selected. If the AUI port is
(TTL/CMOS) manually selected, the MC68160A will not produce link pulses for the TP port.
If APORT is high, TPEN is an output which will indicate which port has been automatically
selected by driving TPEN low (for AUI) or high (for TP). In its output mode TPEN can sink
10 mA in the low output state and source 10 mA in the high output state. (See Pin 9
Description.)
Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to
resume normal operation. The power consumption is minimized in the circuitry associated
with the unselected port. In the standby mode, this pin is driven to the high impedance state.
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Freescale SMeCm68i1c6o0nAductor, Inc.
Figure 3. Test Load B1
Figure 4. Test Load B2
Device V1
39 Ω
39 Ω
RCM
1.0 k Ω
+
VCMD
–
Device
Figure 5. Test Load B3
39 Ω
39 Ω
100 Ω
Device
39 Ω
39 Ω
RCM
10 kΩ
+
VCMD
–
NOTE: A total of 50 Ω per driver output is required for proper series line termination. This is realized with the
39 Ω external resistors shown in Figures 3, 4 and 5, together with the internal driver output resistance.
Figure 6. AUI Common Mode Termination
39 Ω IO
VCM
39 Ω
–
VDIFF
+
Figure 7. AUI Differential Output
Short Circuit Current
IOD
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