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ATtiny441 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 ATtiny441은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 ATtiny441 기능
기능 8-bit AVR Microcontroller
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고


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ATtiny441 데이터시트, 핀배열, 회로
ATtiny441/ATtiny841
8-bit AVR Microcontroller with 4/8K Bytes In-System
Programmable Flash
Features
DATASHEET
High Performance, Low Power Atmel® AVR® 8-bit Microcontroller
Advanced RISC Architecture
120 Powerful Instructions – Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
Non-volatile Program and Data Memories
4/8K Bytes of In-System Programmable Flash Program Memory
Endurance: 10,000 Write/Erase Cycles
256/512 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
256/512 Bytes Internal SRAM
Data Retention: 20 Years at 85oC / 100 Years at 25oC
Programming Lock for Self-Programming Flash & EEPROM Data Security
Peripheral Features
One 8-bit and Two 16-bit Timer/Counters with Two PWM Channels, Each
Programmable Ultra Low Power Watchdog Timer
10-bit Analog to Digital Converter
12 External and 5 Internal, Single-ended Input Channels
46 Differential ADC Channel Pairs with Programmable Gain (1x / 20x / 100x)
Two On-chip Analog Comparators
Two Full Duplex USARTs with Start Frame Detection
Master/Slave SPI Serial Interface
Slave I2C Serial Interface
Special Microcontroller Features
Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes
Enhanced Power-on Reset Circuit
Programmable Brown-out Detection Circuit with Supply Voltage Sampling
External and Internal Interrupt Sources
Pin Change Interrupt on 12 Pins
Calibrated 8MHz Oscillator with Temperature Calibration Option
Calibrated 32kHz Ultra Low Power Oscillator
High-Current Drive Capability on 2 I/O Pins
I/O and Packages
14-pin SOIC, 20-pad MLF/QFN and 20-pad VQFN
12 Programmable I/O Lines
Speed Grade
0 – 2 MHz @ 1.7 – 1.8V
0 – 4 MHz @ 1.8 – 5.5V
0 – 10 MHz @ 2.7 – 5.5V
0 – 16 MHz @ 4.5 – 5.5V
Low Power Consumption
Active Mode: 0.2 mA at 1.8V and 1MHz
Idle Mode: 30 µA at 1.8V and 1MHz
Power-Down Mode (WDT Enabled): 1.3µA at 1.8V
Power-Down Mode (WDT Disabled): 150nA at 1.8V
8495H–AVR–05/2014




ATtiny441 pdf, 반도체, 판매, 대치품
2. Overview
ATtiny441/841 is a low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the ATtiny441/841 achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing speed.
Figure 2-1. Block Diagram
VCC RESET GND
POWER
SUPERVISION:
POR
BOD
RESET
CALIBRATED ULP
OSCILLATOR
WATCHDOG
TIMER
PROGRAM
MEMORY
(FLASH)
DEBUG
INTERFACE
ON-CHIP
DEBUGGER
EEPROM
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
DATA
MEMORY
(SRAM)
CPU CORE
PORT A
8-BIT DATA BUS
ISP
INTERFACE
USART
TWO-WIRE
INTERFACE
USART
8-BIT
TIMER/COUNTER
TEMPERATURE
SENSOR
ANALOG
COMPARATOR
ANALOG
COMPARATOR
16-BIT
TIMER/COUNTER
16-BIT
TIMER/COUNTER
VOLTAGE
REFERENCE
MULTIPLEXER
ADC
PORT B
PA[7:0]
PB[3:0]
ATtiny441/841 [DATASHEET]
8495H–AVR–05/2014
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ATtiny441 전자부품, 판매, 대치품
4. CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct
program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and
handle interrupts.
4.1 Architectural Overview
Figure 4-1. Block Diagram of the AVR Architecture
8-BIT DATA BUS
DATA
MEMORY
(SRAM)
PROGRAM
COUNTER
PROGRAM
MEMORY
(FLASH)
INTERRUPT
UNIT
STATUS AND
CONTROL
GENERAL
PURPOSE
REGISTERS
X
Y
Z
INSTRUCTION
REGISTER
ALU
INSTRUCTION
DECODER
CONTROL
LINES
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and
buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables
instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time.
This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from
the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for
look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described
later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register
operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect
information about the result of the operation.
ATtiny441/841 [DATASHEET]
8495H–AVR–05/2014
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