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PDF ATtiny841 Data sheet ( Hoja de datos )
| Número de pieza | ATtiny841 | |
| Descripción | 8-bit AVR Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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ATtiny441/ATtiny841
8-bit AVR Microcontroller with 4/8K Bytes In-System
Programmable Flash
Features
DATASHEET
High Performance, Low Power Atmel® AVR® 8-bit Microcontroller
Advanced RISC Architecture
120 Powerful Instructions – Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
Non-volatile Program and Data Memories
4/8K Bytes of In-System Programmable Flash Program Memory
Endurance: 10,000 Write/Erase Cycles
256/512 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
256/512 Bytes Internal SRAM
Data Retention: 20 Years at 85oC / 100 Years at 25oC
Programming Lock for Self-Programming Flash & EEPROM Data Security
Peripheral Features
One 8-bit and Two 16-bit Timer/Counters with Two PWM Channels, Each
Programmable Ultra Low Power Watchdog Timer
10-bit Analog to Digital Converter
12 External and 5 Internal, Single-ended Input Channels
46 Differential ADC Channel Pairs with Programmable Gain (1x / 20x / 100x)
Two On-chip Analog Comparators
Two Full Duplex USARTs with Start Frame Detection
Master/Slave SPI Serial Interface
Slave I2C Serial Interface
Special Microcontroller Features
Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes
Enhanced Power-on Reset Circuit
Programmable Brown-out Detection Circuit with Supply Voltage Sampling
External and Internal Interrupt Sources
Pin Change Interrupt on 12 Pins
Calibrated 8MHz Oscillator with Temperature Calibration Option
Calibrated 32kHz Ultra Low Power Oscillator
High-Current Drive Capability on 2 I/O Pins
I/O and Packages
14-pin SOIC, 20-pad MLF/QFN and 20-pad VQFN
12 Programmable I/O Lines
Speed Grade
0 – 2 MHz @ 1.7 – 1.8V
0 – 4 MHz @ 1.8 – 5.5V
0 – 10 MHz @ 2.7 – 5.5V
0 – 16 MHz @ 4.5 – 5.5V
Low Power Consumption
Active Mode: 0.2 mA at 1.8V and 1MHz
Idle Mode: 30 µA at 1.8V and 1MHz
Power-Down Mode (WDT Enabled): 1.3µA at 1.8V
Power-Down Mode (WDT Disabled): 150nA at 1.8V
8495H–AVR–05/2014
1 page  
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
ATtiny441/841 provides the following features:
4K/8K bytes of in-system programmable Flash
256/512 bytes of SRAM data memory
256/512 bytes of EEPROM data memory
12 general purpose I/O lines
32 general purpose working registers
One 8-bit timer/counter with two PWM channels
Two 16-bit timer/counters with two PWM channels
Internal and external interrupts
One 10-bit ADC with 5 internal and 12 external channels
One ultra-low power, programmable watchdog timer with internal oscillator
Two programmable USARTs with start frame detection
Slave Two-Wire Interface (TWI)
Master/slave Serial Peripheral Interface (SPI)
Calibrated 8MHz oscillator
Calibrated 32kHz, ultra low power oscillator
Four software selectable power saving modes.
The device includes the following modes for saving power:
Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt
system to continue functioning
ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all I/O
modules except the ADC
Power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or
hardware reset
Standby mode: the oscillator is running while the rest of the device is sleeping, allowing very fast start-up
combined with low power consumption
The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash program memory can
be re-programmed in-system through a serial interface, by a conventional non-volatile memory programmer or by an on-
chip boot code, running on the AVR core.
The ATtiny441/841 AVR is supported by a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators and evaluation kits.
ATtiny441/841 [DATASHEET]
8495H–AVR–05/2014
5
5 Page 
Figure 4-5. Single Cycle ALU Operation
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1
T2 T3
T4
4.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a
separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be
written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The
complete list of vectors is shown in “Interrupts” on page 49. The list also determines the priority levels of the different
interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the
External Interrupt Request 0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software
can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt
routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these
interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling
routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one
to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software.
Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding
Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by
order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily
have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be
triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before
any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning
from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be
executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows
how this can be used to avoid interrupts during the timed EEPROM write sequence.
ATtiny441/841 [DATASHEET]
8495H–AVR–05/2014
11
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