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PDF ATtiny40 Data sheet ( Hoja de datos )
| Número de pieza | ATtiny40 | |
| Descripción | 8-bit tinyAVR Microcontroller | |
| Fabricantes | ATMEL Corporation | |
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8-bit Atmel tinyAVR Microcontroller with
4K Bytes In-System Programmable Flash
ATtiny40
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 54 Powerful Instructions – Most Single Clock Cycle Execution
– 16 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 12 MIPS Throughput at 12 MHz
• Non-volatile Program and Data Memories
– 4K Bytes of In-System Programmable Flash Program Memory
– 256 Bytes Internal SRAM
– Flash Write/Erase Cycles: 10,000
– Data Retention: 20 Years at 85oC / 100 Years at 25oC
• Peripheral Features
– One 8-bit Timer/Counter with Two PWM Channels
– One 8/16-bit Timer/Counter
– 10-bit Analog to Digital Converter
• 12 Single-Ended Channels
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Master/Slave SPI Serial Interface
– Slave TWI Serial Interface
• Special Microcontroller Features
– In-System Programmable
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, Stand-by and Power-down Modes
– Enhanced Power-on Reset Circuit
– Internal Calibrated Oscillator
• I/O and Packages
– 20-pin SOIC: 18 Programmable I/O Lines
– 20-pin TSSOP: 18 Programmable I/O Lines
– 20-pad VQFN: 18 Programmable I/O Lines
• Operating Voltage:
– 1.8 – 5.5V
• Programming Voltage:
– 5V
• Speed Grade
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 8 MHz @ 2.7 – 5.5V
– 0 – 12 MHz @ 4.5 – 5.5V
• Industrial Temperature Range
• Low Power Consumption
– Active Mode:
• 200 µA at 1 MHz and 1.8V
– Idle Mode:
• 25 µA at 1 MHz and 1.8V
– Power-down Mode:
• < 0.1 µA at 1.8V
8263B–AVR–01/2013
1 page  
The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip, in-system
programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile
memory programmer.
The ATtiny40 AVR is supported by a suite of program and system development tools, including macro assemblers
and evaluation kits.
3. General Information
3.1 Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available
for download at http://www.atmel.com/avr.
3.2 Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
Please confirm with the C compiler documentation for more details.
3.3 Capacitive Touch Sensing
Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcon-
trollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition methods.
Touch sensing is easily added to any application by linking the QTouch Library and using the Application Program-
ming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to
retrieve channel information and determine the state of the touch sensor.
The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of
implementation, refer to the QTouch Library User Guide – also available from the Atmel website.
3.4 Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.
3.5 Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcon-
trollers manufactured on the same process technology.
4. CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure cor-
rect program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
5
5 Page 
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pend-
ing interrupts, as shown in the following example.
Assembly Code Example
sei
sleep
; set Global Interrupt Enable
; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
Note: See “Code Examples” on page 5.
4.7.1
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock
cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle
period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and
this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction
is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt exe-
cution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the
selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program
Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG
is set.
4.8 Register Description
4.8.1 CCP – Configuration Change Protection Register
Bit 7 6 5 4 3 2 1 0
0x3C
CCP[7:0]
CCP
Read/Write
WW
WWWW
WW
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:0 – CCP[7:0]: Configuration Change Protection
In order to change the contents of a protected I/O register the CCP register must first be written with the correct
signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction
cycles. All interrupts are ignored during these cycles. After these cycles interrupts are automatically handled again
by the CPU, and any pending interrupts will be executed according to their priority.
When the protected I/O register signature is written, CCP0 will read as one as long as the protected feature is
enabled, while CCP[7:1] will always read as zero.
Table 4-1 shows the signatures that are in recognised.
Table 4-1.
Signature
0xD8
Signatures Recognised by the Configuration Change Protection Register
Group
IOREG: CLKMSR, CLKPSR, WDTCSR(1), MCUCR(2)
Description
Protected I/O register
Notes: 1. Only WDE and WDP[3:0] bits are protected in WDTCSR.
2. Only BODS bit is protected in MCUCR.
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
11
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