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PDF ATmega168PB Data sheet ( Hoja de datos )
| Número de pieza | ATmega168PB | |
| Descripción | AVR 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Atmel AVR 8-bit Microcontroller with 4/8/16KBytes
In-System Programmable Flash
ATmega48PB/88PB/168PB
DATASHEET
Features
High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family
Advanced RISC Architecture
̶ 131 Powerful Instructions – Most Single Clock Cycle Execution
̶ 32 x 8 General Purpose Working Registers
̶ Fully Static Operation
̶ Up to 20 MIPS Throughput at 20MHz
̶ On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments
̶ 4/8/16KBytes of In-System Self-Programmable Flash program memory
̶ 256/512/512Bytes EEPROM
̶ 512/1K/1KBytes Internal SRAM
̶ Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
̶ Data retention: 20 years at 85C/100 years at 25C
̶ Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
̶ Programming Lock for Software Security
Atmel® QTouch® library support
̶ Capacitive touch buttons, sliders and wheels
̶ QTouch and QMatrix acquisition
̶ Up to 64 sense channels
Peripheral Features
̶ Two 8-bit Timer/Counters (TC) with Separate Prescaler and Compare Mode
̶ 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
̶ Real Time Counter (RTC) with Separate Oscillator
̶ Six Pulse Width Modulation (PWM) channels
̶ 8-channel 10-bit ADC with temperature measurement
̶ Programmable Serial USART with start-of-frame detection
̶ Master/Slave SPI Serial Interface
̶ Byte-oriented Two-Wire Serial Interface (Phillips I2C compatible)
̶ Programmable Watchdog Timer (WDT) with separate on-chip oscillator
̶ On-chip Analog Comparator
̶ Interrupt and Wake-up on Pin Change
256-channel capacitive touch and proximity sensing
Special Microcontroller Features
̶ Power-on Reset (POR) and Programmable Brown-out Detection (BOD)
̶ Internal calibrated oscillator
̶ External and internal interrupt sources
̶ Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
̶ Unique Device ID
I/O and Packages
̶ 27 Programmable I/O Lines
̶ 32-lead TQFP and 32-pad VFQFN
Operating Voltage: 1.8 - 5.5V
Temperature Range: -40C to 105C
Speed Grade: 0 - [email protected] - 5.5V, 0 - [email protected] - 5.5.V, 0 - 20MHz @ 4.5 - 5.5V
Power Consumption at 1MHz, 1.8V, 25C
̶ Active Mode: 0.35mA
̶ Power-down Mode: 0.23µA
̶ Power-save Mode: <1.4µA (Including 32kHz RTC)
Atmel-42176E–8-bit AVR-ATmega48PB-88PB-168PB–10/2015
1 page  
2.1 Pin Descriptions
2.1.1 VCC
Digital supply voltage.
2.1.2 GND
Ground.
2.1.3
Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and
input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1 input for the
Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page 82 and ”System
Clock and Clock Options” on page 29.
2.1.4
Port C (PC5:0)
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5...0 output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
2.1.5
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6
differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the
minimum pulse length will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to
generate a Reset.
The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page 85.
2.1.6
Port D (PD7:0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page 87.
2.1.7
Port E(PE3:0)
Port E is an 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that
ATmega48PB/88PB/168PB [DATASHEET]
Atmel-42176E–8-bit AVR-ATmega48PB-88PB-168PB_Datasheet_10/2015
5
5 Page 
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two
operands are output from the Register File, the operation is executed, and the result is stored back in the Register
File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address
contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application Program
section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total
SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before
subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data
SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the
Register File, 0x20 - 0x5F. In addition, the ATmega48PB/88PB/168PB has Extended I/O space from 0x60 - 0xFF
in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
8.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-
functions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
8.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
ATmega48PB/88PB/168PB [DATASHEET]
Atmel-42176E–8-bit AVR-ATmega48PB-88PB-168PB_Datasheet_10/2015
11
11 Page | ||
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| PDF Descargar | [ Datasheet ATmega168PB.PDF ] | |
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