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부품번호 | 74HC132 기능 |
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기능 | Quad 2-input NAND Schmitt trigger | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 19 페이지수
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
Rev. 4 — 1 December 2015
Product data sheet
1. General description
The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs
include clamp diodes. This enables the use of current limiting resistors to interface inputs
to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input
signals into sharply defined jitter-free output signals.
2. Features and benefits
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Wave and pulse shapers
Astable multivibrators
Monostable multivibrators
NXP Semiconductors
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
IIK input clamping current
IOK output clamping current
IO output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
0.5
[1] -
[1] -
-
+7 V
20 mA
20 mA
25 mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
SO14, and (T)SSOP14 packages
-
50
65
[2] -
50
-
+150
500
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
9. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
VCC
VI
VO
Tamb
supply voltage
input voltage
output voltage
ambient temperature
74HC132
Min Typ Max
2.0 5.0 6.0
0 - VCC
0 - VCC
40 +25 +125
74HCT132
Min Typ Max
4.5 5.0 5.5
0 - VCC
0 - VCC
40 +25 +125
Unit
V
V
V
C
74HC_HCT132
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 1 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 19
4페이지 NXP Semiconductors
12. Waveforms
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
9,
Q$Q%LQSXW
*1'
92+
Q<RXWSXW
92/
90
W3+/
9<
W7+/
90
9;
W3/+
W7/+
Fig 5.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Input to output propagation delays
DDL
Table 8. Measurement points
Type
Input
74HC132
74HCT132
VM
0.5VCC
1.3 V
Output
VM
0.5VCC
1.3 V
VX
0.1VCC
0.1VCC
VY
0.9VCC
0.9VCC
9,
QHJDWLYH
SXOVH
*1'
9,
SRVLWLYH
SXOVH
*1'
90
WI
WU
90
9,
*
57
W:
W:
9&&
'87
90
WU
WI
90
92
&/
DDK
Fig 6.
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Test circuit for measuring switching times
74HC_HCT132
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 1 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
7 of 19
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |