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PDF ATxmega64D3 Data sheet ( Hoja de datos )
| Número de pieza | ATxmega64D3 | |
| Descripción | 8/16-bit Atmel AVR XMEGA D3 Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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8/16-bit Atmel AVR XMEGA D3 Microcontroller
ATxmega32D3 / ATxmega64D3 / ATxmega128D3 /
ATxmega192D3 / ATxmega256D3 / ATxmega384D3
Features
High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
Nonvolatile program and data memories
32K - 384KBytes of in-system self-programmable flash
4K - 8KBytes boot section
1K - 4KBytes EEPROM
4K - 32KBytes internal SRAM
Peripheral features
Four-channel event system
Five 16-bit timer/counters
Four timer/counters with four output compare or input capture channels
One timer/counter with two output compare or input capture channels
High resolution extension on two timer/counters
Advanced waveform extension (AWeX) on one timer/counter
Three USARTs with IrDA support for one USART
Two two-wire interfaces with dual address match (I2C and SMBus compatible)
Two serial peripheral interfaces (SPIs)
CRC-16 (CRC-CCITT) and CRC-32 (IEEE®802.3) generator
16-bit real time counter (RTC) with separate oscillator
One sixteen-channel, 12-bit, 300ksps Analog to Digital Converter
Two Analog Comparators with window compare function, and current sources
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
Atmel QTouch® library support
Capacitive touch buttons, sliders and wheels
Special microcontroller features
Power-on reset and programmable brown-out detection
Internal and external clock options with PLL and prescaler
Programmable multilevel interrupt controller
Five sleep modes
Programming and debug interface
PDI (program and debug interface)
I/O and packages
50 programmable I/O pins
64-lead TQFP
64-pad QFN
Operating voltage
1.6 – 3.6V
Operating frequency
0 – 12MHz from 1.6V
0 – 32MHz from 2.7V
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
1 page  
2. Pinout/block Diagram
Figure 2-1. Block Diagram and Pinout
Power
Ground
Digital function
Analog function /Oscillators
Programming, debug, test
External clock /Crystal pins
General Purpose I /O
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GND
VCC
PC0
1
2
3
4 AREF
5 ADC
AC0:1
6
7
8
AREF
9
10
11
12
13
14
15
16
Port R
XOSC
OSC/CLK
Control
Sleep
Controller
DATA BUS
Internal
oscillators
Watchdog
Power
oscillator Supervision
Real Time
Counter
Watchdog
Timer
Reset
Controller
48 PF2
47 PF1
46 PF0
45 VCC
44 GND
Event System
Controller
CRC
OCD
Prog/Debug
Interface
Interrupt
Controller
BUS
matrix
Internal
references
FLASH
CPU
EEPROM
SRAM
43 PE7
42 PE6
41 PE5
40 PE4
39 PE3
38 PE2
DATA BUS
EVENT ROUTING NETWORK
37 PE1
36 PE0
35 VCC
34 GND
33 PD7
Port C
Port D
Port E
Port F
Notes: 1. For full details on pinout and alternate pin functions refer to “Pinout and Pin Functions” on page 50.
2. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good
mechanical stability.
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
5
5 Page 
6.4 ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general
purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register
and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the
status register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
6.4.1
Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
Multiplication of unsigned integers
Multiplication of signed integers
Multiplication of a signed integer with an unsigned integer
Multiplication of unsigned fractional numbers
Multiplication of signed fractional numbers
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
6.5 Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
6.6 Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7 Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The Stack Pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATxmega64D3.PDF ] | |
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