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PDF ATxmega384C3 Data sheet ( Hoja de datos )
| Número de pieza | ATxmega384C3 | |
| Descripción | 8/16-bit Atmel XMEGA C3 Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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8/16-bit Atmel XMEGA C3 Microcontroller
ATxmega384C3
Features
High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
Nonvolatile program and data memories
384KBytes of in-system self-programmable flash
8KBytes boot section
4KBytes EEPROM
32KBytes internal SRAM
Peripheral features
Two -channel DMA controller
Four-channel event system
Five 16-bit timer/counters
Four timer/counters with four output compare or input capture channels
One timer/counter with two output compare or input capture channels
High resolution extension on two timer/counters
Advanced waveform extension (AWeX) on one timer/counter
One USB device interface
USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
32 Endpoints with full configuration flexibility
Three USARTs with IrDA support for one USART
Two two-wire interfaces with dual address match (I2C and SMBus compatible)
Two serial peripheral interfaces (SPIs)
AES crypto engine
CRC-16 (CRC-CCITT) and CRC-32 (IEEE®802.3) generator
16-bit real time counter (RTC) with separate oscillator
One sixteen-channel, 12-bit, 300ksps Analog to Digital Converter
Two Analog Comparators with window compare function, and current sources
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
QTouch® library support
Capacitive touch buttons, sliders and wheels
Special microcontroller features
Power-on reset and programmable brown-out detection
Internal and external clock options with PLL and prescaler
Programmable multilevel interrupt controller
Five sleep modes
Programming and debug interface
PDI (program and debug interface)
I/O and packages
50 programmable I/O pins
64-lead TQFP
64-pad QFN
Operating voltage
1.6 – 3.6V
Operating frequency
0 – 12MHz from 1.6V
0 – 32MHz from 2.7V
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
1 page  
3.1 Block Diagram
Figure 3-1. XMEGA C3 Block Diagram
Power
Ground
Digital function
Analog function /Oscillators
Programming, debug,
External clock /Crystal pins
General Purpose I /O
PA[0..7]
PB[0..7]
ACA
PORT A (8)
ADCA
AREFA
VCC/10
Int. Refs.
Tempref
AREFB
PORT B (8)
PR[0..1]
XTAL1
XTAL2
PORT R (2)
Event System
Controller
DMA
Controller
Real Time
Counter
DATA BUS
SRAM
BUS Matrix
AES
CRC
CPU
NVM Controller
Flash
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Sleep
Controller
Prog/Debug
Controller
OCD
Interrupt
Controller
EEPROM
DATA BUS
EVENT ROUTING NETWORK
Watchdog
Oscillator
Watchdog
Timer
Power
Supervision
POR/BOD &
RESET
PDI
TCF0
PORT C (8)
PC[0..7]
PORT D (8)
PD[0..7]
PORT E (8)
To Clock
Generator
TOSC1
TOSC2
PE[0..7]
VCC
GND
RESET/
PDI_CLK
PDI_DATA
PF[0..7]
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
5
5 Page 
7. Memories
7.1 Features
• Flash program memory
– One linear address space
– In-system programmable
– Self-programming and boot loader support
– Application section for application code
– Application table section for application code or data storage
– Boot section for application code or boot loader code
– Separate read/write protection lock bits for all sections
– Built in fast CRC check of a selectable flash program memory section
• Data memory
– One linear address space
– Single-cycle access from CPU
– SRAM
– EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
– I/O memory
Configuration and status registers for all peripherals and modules
Four bit-accessible general purpose registers for global variables or flags
– Bus arbitration
Deterministic priority handling between CPU, DMA controller, and other bus masters
– Separate buses for SRAM, EEPROM and I/O memory
Simultaneous bus access for CPU and DMA controller
• Production signature row memory for factory programmed data
– ID for each microcontroller device type
– Serial number for each device
– Calibration bytes for factory calibrated peripherals
• User signature row
– One flash page in size
– Can be read and written from software
– Content is kept after chip erase
7.2 Overview
The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code
can reside only in the program memory, while data can be stored in the program memory and the data memory. The data
memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and
require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write
operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has a
Flash memory signature row for calibration data, device identification, serial number, etc.
7.3 Flash Program Memory
The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The
flash memory can be accessed for read and write from an external programmer through the PDI or from application
software running in the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATxmega384C3.PDF ] | |
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