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PDF ATxmega128B3 Data sheet ( Hoja de datos )
| Número de pieza | ATxmega128B3 | |
| Descripción | 8/16-bit Atmel XMEGA B3 Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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8/16-bit Atmel XMEGA B3 Microcontroller
ATxmega128B3 / ATxmega64B3
Features
z High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
z Nonvolatile program and data memories
z 64K - 128KBytes of in-system self-programmable flash
z 4K - 8KBytes boot section
z 2KBytes EEPROM
z 4K - 8KBytes internal SRAM
z Peripheral Features
z Two-channel DMA controller
z Four-channel event system
z Two 16-bit timer/counters
z One timer/counters with 4 output compare or input capture channels
z One timer/counter with 2 output compare or input capture channels
z High resolution extensions one timer/counter
z Advanced waveform extension (AWeX) on one timer/counter
z Split mode on two timer/counters
z One USB device interface
z USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
z 32 Endpoints with full configuration flexibility
z One USARTs with IrDA support for one USART
z AES and DES crypto engine
z CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator
z One two-wire interface with dual address match (I2C and SMBus compatible)
z One serial peripheral interface (SPI)
z 16-bit Real Time Counter (RTC) with separate oscillator
z Liquid Crystal Display
z Up to 4x25 segment driver
z Built in contrast control
z ASCII character mapping
z Flexible SWAP of segment and common terminals buses
z One eight-channel, 12-bit, 300 thousand SPS Analog to Digital Converters
z Two Analog Comparators with window compare function, and current source feature
z External interrupts on all General Purpose I/O pins
z Programmable watchdog timer with separate on-chip ultra low power oscillator
z QTouch® library support
z Capacitive touch buttons, sliders and wheels
z Special microcontroller features
z Power-on reset and programmable brown-out detection
z Internal and external clock options with PLL
z Programmable multilevel interrupt controller
z Five sleep modes
z Programming and debug interfaces
z JTAG (IEEE 1149.1 Compliant) interface, including boundary scan
z PDI (Program and Debug Interface)
z I/O and Packages
z 36 Programmable I/O pins
z 64-lead TQFP
z 64-pad QFN
z 64-pad DRQFN
Atmel-8074E–AVR–ATxmega 128B3 - 64B3_datasheet-09/2014
1 page  
2.2 Pinout – DRQFN
Figure 2-2. DRQFN pinout for ATxmega128B3
Top view
Bottom view
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
A25
B22
A24
B21
A23
B20
A22
B19
A21
B18
A20
B17
A19
B16
A18
A25
B22
A24
B21
A23
B20
A22
B19
A21
B18
A20
B17
A19
B16
A18
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
Table 2-1. DRQFN pinout for ATxmega128B3
Pin Function
Pin Function
A1 PC0
A9 PG0/SEG24
B1 PC1
B8 VCC
A2 PC2
A10 PG2/SEG22
B2 PC3
B9 PG1/SEG23
A3 PC4
A11 PG3/SEG21
B3 PC5
B10 PG4/SEG20
A4 PC6
A12 PG5/SEG19
B4 GND
B11 PG6/SEG18
A5 PC7
A13 PG7/SEG17
B5 PD0
B12 PM0/SEG16
A6 VCC
A14 PM1/SEG15
B6 PDI/RESET
B13 PM2/SEG14
A7 PD1
A15 PM3/SEG13
B7 PDI
B14 PM5/SEG11
A8 GND
A16 PM4/SEG12
B15 PM7/SEG9
A17 PM6/SEG10
Pin Function
A18 SEG7
B16 SEG8
A19 SEG6
B17 SEG5
A20 SEG4
B18 SEG3
A21 SEG2
B19 SEG1
A22 SEG0
B20 GND
A23 VCC
B21 BIAS1
A24 BIAS2
B22 VLCD
A25 CAPL
Pin Function
A26 CAPH
B23 COM0
A27 COM1
B24 COM2
A28 COM3
B25 PR0
A29 PR1
B26 AGND
A30 PB0
B27 AVCC
A31 PB1
B28 PB2
A32 PB3
B29 PB4
A33 PB5
B30 PB7
A34 PB6
XMEGA B3 [DATASHEET]
Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014
5
5 Page 
6.5 Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
6.6 Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7 Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
6.8 Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
z One 8-bit output operand and one 8-bit result input
z Two 8-bit output operands and one 8-bit result input
z Two 8-bit output operands and one 16-bit result input
z One 16-bit output operand and one 16-bit result input
XMEGA B3 [DATASHEET]
Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATxmega128B3.PDF ] | |
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