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PDF ATxmega32A4U Data sheet ( Hoja de datos )
| Número de pieza | ATxmega32A4U | |
| Descripción | 8/16-bit Atmel XMEGA Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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8/16-bit Atmel XMEGA Microcontroller
ATxmega128A4U / ATxmega64A4U /
ATxmega32A4U / ATxmega16A4U
Features
z High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
z Nonvolatile program and data memories
z 16K - 128KB of in-system self-programmable flash
z 4K - 8KB boot section
z 1K - 2KB EEPROM
z 2K - 8KB internal SRAM
z Peripheral Features
z Four-channel DMA controller
z Eight-channel event system
z Five 16-bit timer/counters
z Three timer/counters with 4 output compare or input capture channels
z Two timer/counters with 2 output compare or input capture channels
z High-resolution extensions on all timer/counters
z Advanced waveform extension (AWeX) on one timer/counter
z One USB device interface
z USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
z 32 Endpoints with full configuration flexibility
z Five USARTs with IrDA support for one USART
z Two Two-wire interfaces with dual address match (I2C and SMBus compatible)
z Two serial peripheral interfaces (SPIs)
z AES and DES crypto engine
z CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator
z 16-bit real time counter (RTC) with separate oscillator
z One twelve-channel, 12-bit, 2msps Analog to Digital Converter
z One two-channel, 12-bit, 1msps Digital to Analog Converter
z Two Analog Comparators with window compare function, and current sources
z External interrupts on all general purpose I/O pins
z Programmable watchdog timer with separate on-chip ultra low power oscillator
z QTouch® library support
z Capacitive touch buttons, sliders and wheels
z Special microcontroller features
z Power-on reset and programmable brown-out detection
z Internal and external clock options with PLL and prescaler
z Programmable multilevel interrupt controller
z Five sleep modes
z Programming and debug interfaces
z PDI (program and debug interface)
z I/O and packages
z 34 Programmable I/O pins
z 44 - lead TQFP
z 44 - pad VQFN/QFN
z 49 - ball VFBGA
z Operating voltage
z 1.6 – 3.6V
z Operating frequency
z 0 – 12MHz from 1.6V
z 0 – 32MHz from 2.7V
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
1 page  
Figure 2-2. BGA pinout
A
B
C
D
E
F
G
Top view
1234567
Bottom view
7654321
A
B
C
D
E
F
G
Table 2-1. BGA pinout
1
A PA3
2
AVCC
B PA4
PA1
C PA5
D PB1
E GND
F VCC
G PC1
PA2
PB2
GND
PC0
PC2
3
GND
PA0
PA6
PB3
PC3
PC4
PC5
4
PR1
GND
PA7
PB0
GND
PC6
PC7
5
PR0
RESET/
PDI_CLK
GND
GND
PD4
PD0
GND
6
PDI_DATA
PE2
PE1
PD7
PD5
PD1
VCC
7
PE3
VCC
GND
PE0
PD6
PD3
PD2
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
5
5 Page 
purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a
register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic
operation, the status register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
6.4.1
Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports
different variations of signed and unsigned integer and fractional numbers:
z Multiplication of unsigned integers
z Multiplication of signed integers
z Multiplication of a signed integer with an unsigned integer
z Multiplication of unsigned fractional numbers
z Multiplication of signed fractional numbers
z Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
6.5 Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The
program counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the
general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the
SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write
accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM
can easily be accessed through the five different addressing modes supported in the AVR CPU.
6.6 Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7 Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH
and POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that
pushing data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is
automatically loaded after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed,
it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or
before interrupts are enabled.
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATxmega32A4U.PDF ] | |
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