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ATxmega256A3BU PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ATxmega256A3BU
기능 8/16-bit Atmel XMEGA A3BUMicrocontroller
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ATxmega256A3BU 데이터시트, 핀배열, 회로
Features
8/16-bit Atmel XMEGA A3BUMicrocontroller
ATxmega256A3BU
z High-performance, low-power Atmel®AVR®XMEGA® 8/16-bit Microcontroller
z Nonvolatile program and data memories
z 256KBytes of in-system self-programmable flash
z 8KBytes boot section
z 4KBytes EEPROM
z 16KBytes internal SRAM
z Peripheral features
z Four-channel DMA controller
z Eight-channel event system
z Seven 16-bit timer/counters
z Four timer/counters with four output compare or input capture channels
z Three timer/counters with two output compare or input capture channels
z High resolution extension on all timer/counters
z Advanced waveform extension (AWeX) on one timer/counter
z One USB device interface
z USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
z 32 Endpoints with full configuration flexibility
z Six USARTs with IrDA support for one USART
z Two two-wire interfaces with dual address match (I2C and SMBus compatible)
z Two serial peripheral interfaces (SPIs)
z AES and DES crypto engine
z CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator
z 32-bit real time counter (RTC) with separate oscillator and battery backup system
z Two sixteen-channel, 12-bit, 2msps Analog to Digital Converters
z One two-channel, 12-bit, 1msps Digital to Analog Converter
z Four Analog Comparators with window compare function, and current sources
z External interrupts on all general purpose I/O pins
z Programmable watchdog timer with separate on-chip ultra low power oscillator
z QTouch® library support
z Capacitive touch buttons, sliders and wheels
z Special microcontroller features
z Power-on reset and programmable brown-out detection
z Internal and external clock options with PLL and prescaler
z Programmable multilevel interrupt controller
z Five sleep modes
z Programming and debug interfaces
z JTAG (IEEE 1149.1 compliant) interface, including boundary scan
z PDI (Program and Debug Interface)
z I/O and packages
z 47 programmable I/O pins
z 64-lead TQFP
z 64-pad QFN
z Operating voltage
z 1.6 – 3.6V
z Operating frequency
z 0 – 12MHz from 1.6V
z 0 – 32MHz from 2.7V
Atmel-8362 G-AVR-ATxmega-07/2014




ATxmega256A3BU pdf, 반도체, 판매, 대치품
3. Overview
The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based
on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA device
achieves CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system
designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The XMEGA A3BU devices provide the following features: in-system programmable flash with read-while-write
capabilities; internal EEPROM and SRAM; four-channel DMA controller; eight-channel event system and programmable
multilevel interrupt controller; 47 general purpose I/O lines; 32-bit real-time counter (RTC) with battery backup system;
seven flexible 16-bit Timer/Counters with compare modes and PWM; one full speed USB 2.0 interface; six USARTs; two
two-wire serial interfaces (TWIs); two serial peripheral interfaces (SPIs); AES and DES cryptographic engine; two 16-
channel, 12-bit ADCs with programmable gain; one 2-channel 12-bit DAC; four analog comparators (ACs) with window
mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and
prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The
devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for boundary scan, on-chip
debug and programming.
The XMEGA A3BU devices have five software selectable power saving modes. The idle mode stops the CPU while
allowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The
power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the
next TWI, USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter
continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby
mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup
from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and
the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual
peripheral can optionally be stopped in active mode and idle sleep mode.
Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can
be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use any
interface to download the application program to the flash memory. The boot loader software in the boot flash section will
continue to run while the application flash section is updated, providing true read-while-write operation. By combining an
8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that
provides a highly flexible and cost effective solution for many embedded applications.
All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C
compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
XMEGA A3BU [DATASHEET]
Atmel-8362 G-AVR-ATxmega-07/2014
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ATxmega256A3BU 전자부품, 판매, 대치품
6. AVR CPU
6.1 Features
z 8/16-bit, high-performance Atmel AVR RISC CPU
z 142 instructions
z Hardware multiplier
z 32x8-bit registers directly connected to the ALU
z Stack in RAM
z Stack pointer accessible in I/O memory space
z Direct addressing of up to 16MB of program memory and 16MB of data memory
z True 16/24-bit access to 16/24-bit I/O registers
z Efficient support for 8-, 16-, and 32-bit arithmetic
z Configuration change protection of system-critical features
6.2 Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable
Multilevel Interrupt Controller” on page 28.
6.3 Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.
Figure 6-1. Block diagram of the AVR CPU architecture.
Register File
R31 (ZH)
R30 (ZL)
R29 (YH)
R28 (YL)
R27 (XH)
R25
R26 (XL)
R24
R23 R22
R21 R20
R19 R18
R17 R16
R15 R14
R13 R12
R11 R10
R9 R8
R7 R6
R5 R4
R3 R2
R1 R0
Program
Counter
Flash Program
Memory
Instruction
Register
Instruction
Decode
Stack
Pointer
Status
Register
ALU
Data Memory
XMEGA A3BU [DATASHEET]
Atmel-8362 G-AVR-ATxmega-07/2014
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ATxmega256A3BU

8/16-bit Atmel XMEGA A3BUMicrocontroller

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