1.5 Pin Description
Table 1-1. Atmel AT89LP51RB2/RC2/IC2 Pin Description
Pin Number
VQFP
VQFN PLCC
(1)
PDIP
Symbol
Type Description
I/O P1.5: User-configurable I/O Port 1 bit 5.
I/O MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When
configured as slave, this pin is an output.
1
7
6
P1.5
I/O MOSI: SPI master-out/slave-in (Remap mode). When configured as master, this pin is an output.
When configured as slave, this pin is an input. During In-System Programming, this pin is an
input.
I/O CEX2: Capture/Compare external I/O for PCA module 2.
I/O P1.6: User-configurable I/O Port 1 bit 6.
I/O SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave,
this pin is an input.
2
8
7
P1.6
I/O MISO: SPI master-in/slave-out (Remap mode). When configured as master, this pin is an input.
When configured as slave, this pin is an output. During In-System Programming, this pin is an
output.
I/O CEX3: Capture/Compare external I/O for PCA module 3.
I/O P1.7: User-configurable I/O Port 1 bit 7.
I/O MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When
3
9
8
P1.7
configured as slave, this pin is an input.
I/O SCK: SPI Clock (Remap mode). When configured as master, this pin is an output. When
configured as slave, this pin is an input. During In-System Programming, this pin is an input.
I/O CEX4: Capture/Compare external I/O for PCA module 4.
I/O RST: External Reset input (Reset polarity depends on POL pin. See “External Reset” on page
4 10 9 RST
53.). The RST pin can output a pulse when the internal Watchdog reset or POR is active.
I DCL: Serial Debug Clock input for On-Chip Debug Interface when OCD is enabled.
5
11
10
P3.0
I/O P3.0: User-configurable I/O Port 3 bit 0.
I RXD: Serial Port Receiver Input.
6 12
P4.1
I/O P4.1: User-configurable I/O Port 4bit 1.
I/O SDA: TWI bidirectional Serial Data line.
7
13
11
P3.1
I/O P3.1: User-configurable I/O Port 3 bit 1.
O TXD: Serial Port Transmitter Output.
8
14
12
P3.2
I/O P3.2: User-configurable I/O Port 3 bit 2.
I INT0: External Interrupt 0 Input or Timer 0 Gate Input.
9
15
13
P3.3
I/O P3.3: User-configurable I/O Port 3 bit 3.
I INT1: External Interrupt 1 Input or Timer 1 Gate Input
10
16
14
P3.4
I/O P3.4: User-configurable I/O Port 3 bit 4.
I/O T1: Timer/Counter 0 External input or output.
11
17
15
P3.5
I/O P3.5: User-configurable I/O Port 3 bit 5.
I/O T1: Timer/Counter 1 External input or output.
12
18
16
P3.6
I/O P3.6: User-configurable I/O Port 3 bit 6.
O WR: External memory interface Write Strobe (active-low).
13
19
17
P3.7
I/O P3.7: User-configurable I/O Port 3 bit 7.
O RD: External memory interface Read Strobe (active-low).
I/O P4.7: User-configurable I/O Port 4 bit 7.
14 20 18
P4.7
O XTAL2A: Output from inverting oscillator amplifier A. It may be used as a port pin if the internal
RC oscillator or external clock is selected as the clock source A.
I/O P4.6: User-configurable I/O Port 4 bit 6.
15 21 19 P4.6
I XTAL1A: Input to the inverting oscillator amplifier A and internal clock generation circuits. It may
be used as a port pin if the internal RC oscillator is selected as the clock source A.
4 AT89LP51RB2/RC2/IC2 Preliminary
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AT89LP51RB2/RC2/IC2 Preliminary
AT89LP51RB2/RC2/IC2 also includes a compatibility mode that will enable classic 12 clock per
machine cycle operation for true timing compatibility with the Atmel AT89C51RB2/RC2/IC2.
The AT89LP51RB2/RC2/IC2 retains all of the standard features of the AT89C51RB2/RC2/IC2,
including: 24KB/32KB of In-System Programmable Flash program memory, 256 bytes of RAM,
1152 bytes of expanded RAM, up to 40 I/O lines, three 16-bit timer/counters, a Programmable
Counter Array, a programmable hardware watchdog timer, a keyboard interface, a full-duplex
enhanced serial port, a serial peripheral interface (SPI), on-chip crystal oscillator, and a four-
level, ten-vector interrupt system. A block diagram is shown in Figure 2-1.
In addition, the Atmel® AT89LP51RB2/RC2/IC2 provides a Two-Wire Interface (TWI) for up to
400KB/s serial transfer; a 10-bit, 8-channel Analog-to-Digital Converter (ADC) with temperature
sensor and digital-to-analog (DAC) mode; two analog comparators; and an 8MHz internal
oscillator.
Some standard features on the AT89LP51RB2/RC2/IC2 are enhanced with new modes or oper-
ations. Mode 0 of Timer 0 or Timer 1 acts as a variable 9–16 bit timer/counter and Mode 1 acts
as a 16-bit auto-reload timer/counter. In addition, each timer/counter may independently drive an
8-bit precision pulse width modulation output. Mode 0 (synchronous mode) of the serial port
allows flexibility in the phase/polarity relationship between clock and data.
The I/O ports of the AT89LP51RB2/RC2/IC2 can be independently configured in one of four
operating modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input-
only mode, the ports are tristated. Push-pull output mode provides full CMOS drivers and open-
drain mode provides just a pull-down. Unlike other 8051s, this allows Port 0 to operate with on-
chip pull-ups if desired.
The AT89LP51RB2/RC2/IC2 includes an On-Chip Debug (OCD) interface that allows read-mod-
ify-write capabilities of the system state and program flow control, and programming of the
internal memories. The on-chip Flash may also be programmed through the UART-based boot-
loader or the SPI-based In-System programming interface (ISP).
The TWI and OCD features are not available on the PDIP package. The AT89LP51IC2 is also
not available in the PDIP.
The features of the AT89LP51RB2/RC2/IC2 make it a powerful choice for applications that need
pulse width modulation, high speed I/O, and counting capabilities such as alarms, motor control,
corded phones, and smart card readers.
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