AT89LP51IC2 Datasheet PDF - ATMEL Corporation
| Part Number | AT89LP51IC2 | |
| Description | 8-bit Flash Microcontroller | |
| Manufacturers | ATMEL Corporation | |
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Features
• 8-bit Microcontroller Compatible with 8051 Products
• Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– 12 Clock per Machine Cycle Compatibility Mode
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 16x16 Multiply–Accumulate Unit
– 256 x 8 Internal RAM
– On-chip 1152 Bytes Expanded RAM (ERAM)
• Software Selectable Size (0, 256, 512, 768, 1024 or 1152 Bytes)
– Dual Data Pointers
– 4-level Interrupt Priority
• Nonvolatile Program and Data Memory
– 24KB/32KB of In-System Programmable (ISP) Flash Program Memory
– 512-byte User Signature Array
– Endurance: 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 2KB Boot ROM Contains Low Level Flash Programming Routines and a Default
Serial Bootloader
• Peripheral Features
– Three 16-bit Enhanced Timer/Counters
– Seven 8-bit PWM Outputs
– 16-bit Programmable Counter Array
• High Speed Output, Compare/Capture
• Pulse Width Modulation, Watchdog Timer Capabilities
– Enhanced UART with Automatic Address Recognition and Framing
Error Detection
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Two Wire Interface 400K bit/s
– Programmable Watchdog Timer with Software Reset
– 8 General-purpose Interrupt and Keyboard Interface Pins
• Special Microcontroller Features
– Dual Oscillator Support: Crystal, 32 kHz Crystal, 8 MHz Internal (AT89LP51IC2)
– Two-wire On-Chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Selectable Polarity External Reset Pin
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
– 8-bit Clock Prescaler
• I/O and Packages
– Up to 40 Programmable I/O Lines
– Green (Pb/Halide-free) PLCC44, VQFP44, QFN44. PDIP40
– Configurable I/O Modes
• Quasi-bidirectional (80C51 Style), Input-only (Tristate)
• Push-pull CMOS Output, Open-drain
• Operating Conditions
– 2.4V to 5.5V VCC Voltage Range
– -40° C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4V–5.5V (Single-cycle)
8-bit Flash
Microcontroller
with 24K/32K
bytes Program
Memory
AT89LP51RB2
AT89LP51RC2
AT89LP51IC2
Preliminary
3722A–MICRO–10/11
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AT89LP51RB2/RC2/IC2 Preliminary
Table 1-1. Atmel AT89LP51RB2/RC2/IC2 Pin Description
Pin Number
VQFP
VQFN PLCC
(1)
PDIP
Symbol
Type Description
16 22 20 GND
I Ground
17 23
P4.3
I/O P4.3: User-configurable I/O Port 4bit 3.
I/O DDA: Bidirectional Debug Data line for the On-Chip Debug Interface when OCD is enabled.
18
24
21
P2.0
I/O P2.0: User-configurable I/O Port 2 bit 0.
O A8: External memory interface Address bit 8.
19
25
22
P2.1
I/O P2.1: User-configurable I/O Port 2 bit 1.
O A9: External memory interface Address bit 9.
I/O P2.2: User-configurable I/O Port 2 bit 2.
20 26 23
P2.1
O DA-: DAC negative differential output.
O A10: External memory interface Address bit 10.
I/O P2.3: User-configurable I/O Port 2 bit 3.
21 27 24
P2.3
O DA+-: DAC positive differential output.
O A11: External memory interface Address bit 11.
I/O P2.4: User-configurable I/O Port 2 bit 5.
22 28 25 P2.4
I AIN0: Analog Comparator Input 0.
O A12: External memory interface Address bit 12.
I/O P2.5: User-configurable I/O Port 2 bit 5.
23 29 26 P2.5
I AIN1: Analog Comparator Input 1.
O A13: External memory interface Address bit 13.
I/O P2.6: User-configurable I/O Port 2 bit 6.
24 30 27 P2.6
I AIN2: Analog Comparator Input 2.
O A14: External memory interface Address bit 14.
I/O P2.7: User-configurable I/O Port 2 bit 7.
25 31 28 P2.7
I AIN3: Analog Comparator Input 3.
O A15: External memory interface Address bit 15.
26
32
29
P4.5
I/O P4.5: User-configurable I/O Port 4 bit 5.
O PSEN: External memory interface Program Store Enable (active-low).
27
33
30
P4.4
I/O P4.4: User-configurable I/O Port 4 bit 4.
I/O ALE: External memory interface Address Latch Enable.
28 34
P4.0
I/O
P4.0: User-configurable I/O Port 4 bit 0.
SCL: TWI Serial Clock line. This line is an output in mater mode and an input in slave mode.
29 35 31 POL
I POL: Reset polarity (See “External Reset” on page 53.)
30
36
32
P0.7
I/O P0.7: User-configurable I/O Port 0 bit 7.
I/O AD7: External memory interface Address/Data bit 7.
I/O P0.6: User-configurable I/O Port 0 bit 6.
31 37 33 P0.6 I/O AD6: External memory interface Address/Data bit 6.
I ADC6: ADC analog input 6.
I/O P0.5: User-configurable I/O Port 0 bit 5.
32 38 34 P0.5 I/O AD5: External memory interface Address/Data bit 5.
I ADC5: ADC analog input 5.
I/O P0.4: User-configurable I/O Port 0 bit 4.
33 39 35 P0.4 I/O AD4: External memory interface Address/Data bit 4.
I ADC4: ADC analog input 4.
I/O P0.3: User-configurable I/O Port 0 bit 3.
34 40 36 P0.3 I/O AD3: External memory interface Address/Data bit 3.
I ADC3: ADC analog input 3.
3722A–MICRO–10/11
5
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ AT89LP51IC2.PDF Datasheet ] | |
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