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AT89LP3240 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 AT89LP3240
기능 8-bit Microcontroller
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AT89LP3240 데이터시트 및 AT89LP3240 PDF

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AT89LP3240 pdf, 반도체, 판매, 대치품
1.5 Pin Description
Table 1-1. AT89LP3240/6440 Pin Description
Pin Number
TQFP PLCC PDIP VQFN Symbol Type
I/O
1
7
6
1
P1.5
I/O
I
I/O
2
8
7
2
P1.6
I/O
I
I/O
3
9
8
3
P1.7
I/O
I
4 10 9
I/O
4 P4.2 I
I
5
11 10
5
P3.0
I/O
I
6 12
6 VDD I
I/O
7 13 11 7 P3.1
O
8
14 12
8
P3.2
I/O
I
9
15 13
9
P3.3
I/O
I
I/O
10 16 14 10 P3.4
I/O
I/O
11 17 15 11 P3.5
I/O
I/O
12 18 16 12 P3.6
O
I/O
13 19 17 13 P3.7
O
I/O
O
14 20 18 14 P4.1
O
I/O
I/O
I
15 21 19 15 P4.0
I/O
16 22 N/A 16 GND
I
Description
P1.5: User-configurable I/O Port 1 bit 5.
MOSI: SPI master-out/slave-in. When configured as master, this pin is an output.
When configured as slave, this pin is an input.
GPI5: General-purpose Interrupt input 5.
P1.6: User-configurable I/O Port 1 bit 6.
MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When
configured as slave, this pin is an output.
GPI6: General-purpose Interrupt input 6.
P1.7: User-configurable I/O Port 1 bit 7.
SCK: SPI Clock. When configured as master, this pin is an output. When configured
as slave, this pin is an input.
GPI7: General-purpose Interrupt input 7.
P4.2: User-configurable I/O Port 4 bit 2 (if Reset Fuse is disabled).
RST: External Active-Low Reset input (if Reset Fuse is enabled. See “External
Reset” on page 35.).
DCL: Serial Clock input for On-Chip Debug Interface when OCD is enabled.
P3.0: User-configurable I/O Port 3 bit 0.
RXD: Serial Port Receiver Input.
Supply Voltage
P3.1: User-configurable I/O Port 3 bit 1.
TXD: Serial Port Transmitter Output.
P3.2: User-configurable I/O Port 3 bit 2.
INT0: External Interrupt 0 Input or Timer 0 Gate Input.
P3.3: User-configurable I/O Port 3 bit 3.
INT1: External Interrupt 1 Input or Timer 1 Gate Input
P3.4: User-configurable I/O Port 3 bit 4.
T1: Timer/Counter 0 External input or PWM output.
P3.5: User-configurable I/O Port 3 bit 5.
T1: Timer/Counter 1 External input or PWM output.
P3.6: User-configurable I/O Port 3 bit 6.
WR: External memory interface Write Strobe (active-low).
P3.7: User-configurable I/O Port 3 bit 7.
RD: External memory interface Read Strobe (active-low).
P4.1: User-configurable I/O Port 4 bit 1.
XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the
internal RC oscillator is selected as the clock source.
CLKOUT: When the internal RC oscillator is selected as the clock source, may be
used to output the internal clock divided by 2.
DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and
the external clock is selected as the clock source.
P4.0: User-configurable I/O Port 4 bit 0.
XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits.
It may be used as a port pin if the internal RC oscillator is selected as the clock
source.
DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and
the internal RC oscillator is selected as the clock source.
Ground
4 AT89LP3240/6440
3706C–MICRO–2/11

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AT89LP3240 전자부품, 판매, 대치품
AT89LP3240/6440
Timer 0 and Timer 1 in the AT89LP3240/6440 are enhanced with two new modes. Mode 0 can
be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit
auto-reload timer/counter. In addition, the timer/counters may each independently drive an 8-bit
precision pulse width modulation output.
Timer 2 on the AT89LP3240/6440 serves as a 16-bit time base for a 4-channel Compare/Cap-
ture Array with up to four multi-phasic, variable precision (up to 16-bit) PWM outputs.
The enhanced UART of the AT89LP3240/6440 includes Framing Error Detection and Automatic
Address Recognition. In addition, enhancements to Mode 0 allow hardware accelerated emula-
tion of half-duplex SPI or Two Wire interfaces.
The I/O ports of the AT89LP3240/6440 can be independently configured in one of four operating
modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input-only mode,
the ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode
provides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an inter-
rupt using the general-purpose interrupt interface.
2.1 Block Diagram
Figure 2-1. AT89LP3240/6440 Block Diagram
32K/64K Bytes
Flash Code
8K Bytes
Flash Data
256 Bytes
RAM
4K Bytes
ERAM
XRAM
Interface
8051 Single Cycle CPU
Crystal or
Resonator
Port 0
Configurable I/O
Port 1
Configurable I/O
Port 2
Configurable I/O
Port 3
Configurable I/O
Port 4
Configurable I/O
Configurable
Oscillator
On-Chip
Debug
Watchdog
Timer
General-purpose
Interrupt
Dual Data
Pointers
Multiply
Accumulate
(16 x 16)
POR
BOD
Internal
RC Oscillator
UART
SPI
TWI
Timer 0
Timer 1
Timer 2
Compare/
Capture Array
Dual Analog
Comparators
8-channel 10-bit
ADC/DAC
8
3706C–MICRO–2/11
7

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