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AT89LP51 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AT89LP51
기능 8-bit Microcontroller
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AT89LP51 데이터시트, 핀배열, 회로
Features
8-bit Microcontroller Compatible with 8051 Products
Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– 12 Clock per Machine Cycle Compatibility Mode
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 256 x 8 Internal RAM
– External Data/Program Memory Interface
– Dual Data Pointers
– 4-level Interrupt Priority
Nonvolatile Program and Data Memory
– 4K/8K Bytes of In-System Programmable (ISP) Flash Program Memory
– 256 Bytes of Flash Data Memory
– 256-byte User Signature Array
– Endurance: 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 64-byte Fast Page Programming Mode
– 3-level Program Memory Lock for Software Security
– In-Application Programming of Program Memory
Peripheral Features
– Three 16-bit Timer/Counters with Clock Out Modes
– Enhanced UART
• Automatic Address Recognition
• Framing Error Detection
• SPI and TWI Emulation Modes
– Programmable Watchdog Timer with Software Reset and Prescaler
Special Microcontroller Features
– Brown-out Detection and Power-on Reset with Power-off Flag
– Selectable Polarity External Reset Pin
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
– Internal 1.8432 MHz Auxiliary Oscillator
I/O and Packages
– Up to 36 Programmable I/O Lines
– Green (Pb/Halide-free) Packages
• 40-lead PDIP
• 44-lead TQFP/PLCC
• 44-pad VQFN/MLF
– Configurable Port Modes (per 8-bit port)
• Quasi-bidirectional (80C51 Style)
• Input-only (Tristate)
• Push-pull CMOS Output
• Open-drain
Operating Conditions
– 2.4V to 5.5V VCC Voltage Range
– -40° C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4V–5.5V
– 0 to 25 MHz @ 4.5V–5.5V
8-bit
Microcontroller
with 4K/8K
Bytes In-System
Programmable
Flash
AT89LP51
AT89LP52
3709D–MICRO–12/11




AT89LP51 pdf, 반도체, 판매, 대치품
1.5 Pin Description
Table 1-1. AT89LP51/52 Pin Description
Pin Number
TQFP PLCC PDIP VQFN Symbol Type
I/O
1
7
6
1
P1.5
I/O
I/O
2
8
7
2
P1.6
I/O
I/O
3
9
8
3
P1.7
I/O
4 10 9
4
RST
I/O
5
11 10
5
P3.0
I/O
I
6 12
6
NC
I/O
7 13 11 7 P3.1
O
8
14 12
8
P3.2
I/O
I
9
15 13
9
P3.3
I/O
I
I/O
10 16 14 10 P3.4
I/O
I/O
11 17 15 1 P3.5
I/O
I/O
12 18 16 12 P3.6
O
I/O
13 19 17 13 P3.7
O
I/O
14 20 18 14 P4.7
O
I/O
15 21 19 15 P4.6
I
16 22 20 16 GND
I
17 23
17
NC
18
24
21
18
P2.0
I/O
O
19
25
22
19
P2.1
I/O
O
20
26
23
20
P2.1
I/O
O
Description
P1.5: I/O Port 1 bit 5.
MOSI: SPI master-out/slave-in. In UART SPI mode this pin is an output. During In-
System Programming, this pin is an input.
P1.6: I/O Port 1 bit 6.
MISO: SPI master-in/slave-out. In UART SPI mode this pin is an input. During In-
System Programming, this pin is an output.
P1.7: I/O Port 1 bit 7.
SCK: SPI Clock. In UART SPI mode this pin is an output. During In-System
Programming, this pin is an input.
RST: External Reset input (Reset polarity depends on POL pin. See “External Reset”
on page 33.). The RST pin can output a pulse when the internal Watchdog reset is
active.
P3.0: I/O Port 3 bit 0.
RXD: Serial Port Receiver Input.
Not internally connected
P3.1: I/O Port 3 bit 1.
TXD: Serial Port Transmitter Output.
P3.2: I/O Port 3 bit 2.
INT0: External Interrupt 0 Input or Timer 0 Gate Input.
P3.3: I/O Port 3 bit 3.
INT1: External Interrupt 1 Input or Timer 1 Gate Input
P3.4: I/O Port 3 bit 4.
T1: Timer/Counter 0 External input or output.
P3.5: I/O Port 3 bit 5.
T1: Timer/Counter 1 External input or output.
P3.6: I/O Port 3 bit 6.
WR: External memory interface Write Strobe (active-low).
P3.7: I/O Port 3 bit 7.
RD: External memory interface Read Strobe (active-low).
P4.7: I/O Port 4 bit 7.
XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the
internal RC oscillator or external clock is selected as the clock source.
P4.6: I/O Port 4 bit 6.
XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits.
It may be used as a port pin if the internal RC oscillator is selected as the clock
source.
Ground
Not internally connected
P2.0: I/O Port 2 bit 0.
A8: External memory interface Address bit 8.
P2.1: I/O Port 2 bit 1.
A9: External memory interface Address bit 9.
P2.2: I/O Port 2 bit 2.
A10: External memory interface Address bit 10.
4 AT89LP51/52
3709D–MICRO–12/11

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AT89LP51 전자부품, 판매, 대치품
AT89LP51/52
2.1 Block Diagram
Figure 2-1. AT89LP51/52 Block Diagram
4K/8K Bytes
Flash Code
256 Bytes
Flash Data
256 Bytes
RAM
XRAM
Interface
Crystal or
Resonator
8051 Single Cycle CPU
with 12-cycle Compatibility
Port 0
Configurable I/O
UART
Port 1
Configurable I/O
16-bit Timer 0
16-bit Timer 1
Port 2
Configurable I/O
16-bit Timer 2
Port 3
Configurable I/O
Watchdog
Timer
Port 4
Configurable I/O
POR
BOD
Configurable
Oscillator
RC Auxiliary
Oscillator
2.2 System Configuration
The AT89LP51/52 supports several system configuration options. Nonvolatile options are set
through user fuses that must be programmed through the flash programming interface. Volatile
options are controlled by software through individual bits of special function registers (SFRs).
The AT89LP51/52 must be properly configured before correct operation can occur.
2.2.1
Fuse Options
Table 2-1 lists the fusable options for the AT89LP51/52. These options maintain their state even
when the device is powered off, but can only be changed with an external device programmer.
For more information, see Section 17.7 “User Configuration Fuses” on page 86.
3709D–MICRO–12/11
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