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PL520-00 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 PL520-00
기능 Low Phase Noise VCXO
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PL520-00 데이터시트, 핀배열, 회로
PL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
FE AT UR E S
100MHz to 200MHz Fundamental Mode Crystal.
Output range: 100 200MHz (no multiplication),
200 400MHz (2x multiplier), 400 700MHz (4x
multiplier), or 800MHz 1GHz (LVDS output
only for 8x multiplier).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
DESCRIPTION
PL520-00 is a VCXO IC specifically designed to pull
high frequency fundamental crystals. Its design was
optimized to tolerate higher limits of interelectrodes
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input.
BLOCK DIAGRAM
SEL
VCON Oscillator
Amplifier
XIN
w/
integrated
varicaps
XOUT
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
Q
Q
PL520-00
DIE SPECIFICATIONS
Name
Value
Size 65 x 62 mil
Reverse side
GND
Pad dimensions
80 m icron x 80 micron
Th ic kn e s s
10 mil
DIE CONFIGURATION
65 mil
25 24 23 22 21 20 19 18
XIN 26
XOUT 27
Die ID:
A1919-19A
SEL3^ 28
SEL2^ 29
OE
30
CTRL
VCON 31
C502A
12345 6 78
(1550,1475)
17 GNDBUF
16 CMOS
15 LVDSB
14 PECLB
13 VDDBUF
12 VDDBUF
11 PECL
10 LVDS
9 OE_SEL^
Y (0,0)
X
Note: ^ denotes internal pull up
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
0
0
1
1
OUTSEL0
(Pad #25)
0
1
0
1
Selected Output
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
OE_SELECT
(Pad #9)
0
1 (Default)
OE_CTRL
(Pad #30)
0
1 (Default)
0 (Default)
1
State
Tr i- s t a te
Output enabled
Output enabled
Tr i- s t a te
Pad #9, 18, 25: Bond to GND to set to “0”. No connection results to
“default” setting through internal pull-up.
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9)
is “1”
Logical states defined by CMOS levels if OE_SELECT is “0
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 1




PL520-00 pdf, 반도체, 판매, 대치품
PL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
6. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
155.52MHz
622.08MHz
@10Hz
-75
-75
@100Hz
-95
-95
@1kHz
-125
-110
@10kHz
-140
-125
@100kHz
-145
-120
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
7. CMOS Electrical Characteristics
PARAMETERS
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
SYMBOL
IOH
IOL
IOH
IOL
CONDITIONS
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
MIN.
30
30
10
10
TYP. MAX.
2.4
1.2
UNITS
mA
mA
mA
mA
ns
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 4

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PL520-00 전자부품, 판매, 대치품
PL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
PAD ASSIGNMENT
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
GND
GND
GND
GND
GND
N/C
GND
GNDBUF
OE_SELECT
LVDS
PECL
VDDBUF
VDDBUF
PECLB
LVDSB
CMOS
GNDBUF
OUTSEL1
SEL1
SEL0
VDD
VDD
VDD
VDD
OUTSEL0
XIN
XOUT
SEL3
SEL2
OE_CTRL
VCON
X (m)
248
361
473
587
702
874
1042
1171
1400
1400
1400
1400
1400
1400
1400
1400
1389
1232
1042
854
659
559
459
358
194
109
109
109
109
109
109
Y (m)
109
109
109
109
109
109
109
109
125
259
476
616
716
871
1089
1227
1365
1365
1365
1365
1365
1365
1365
1365
1365
1223
1017
858
646
397
181
Description
Ground.
Ground.
Ground.
Ground.
Ground.
No Connection.
Ground.
Ground, Buffer circuitry.
Used to select between PECL or CMOS logic states
for OE. See Output Selection and Enable table on
page 1. Internal pull up.
LVDS output.
PECL output.
3.3V power supply, Buffer circuitry.
3.3V power supply, Buffer circuitry.
Complementary PECL output.
Complementary LVDS output.
CMOS output
Ground, Buffer Circuitry.
Used to select CMOS, PECL or LVDS output type.
See Output Selection and Enable table on page 1.
Internal pull up.
Used to select multiplication factor. See Frequency
Selection table on page 1. Internal pull up.
Used to select multiplication factor. See Frequency
Selection table on page 1. Internal pull up.
3.3V power supply.
3.3V power supply.
3.3V power supply.
3.3V power supply.
Used to select CMOS, PECL or LVDS output type.
See Output Selection and Enable table on page 1.
Internal pull up.
Crystal input. See crystal specification page 2.
Crystal output. See crystal specification page 2.
Used to select multiplication factor. See Frequency
Selection table on page 1. Internal pull up.
Used to select multiplication factor. See Frequency
Selection table on page 1. Internal pull up.
Used to enable/disable the output(s). See Output
Selection and Enable table on page 1.
Voltage Control input. 0V to 3.3V.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 7

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PL520-00

Low Phase Noise VCXO

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