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PL520-20 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 PL520-20
기능 Low Phase Noise VCXO
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PL520-20 데이터시트, 핀배열, 회로
PL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
FE AT UR E S
100MHz to 200MHz Fundamental Mode Crystals
Output range (no PLL):
100MHz 200MHz (3.3V).
100MHz 170MHz (2.5V).
Low Injection Power for crystal 50uW.
Complementary outputs: CMOS, PECL or LVDS.
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Die thickness is 10 mil.
DESCRIPTION
PL520-20 is a VCXO IC specifically designed to pull
high frequency fundamental crystals. Its design was
optimized to tolerate higher limits of inter-electrode
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability. Its internal
varicaps allow on-chip frequency pulling, controlled
by the VCON input.
BLOCK DIAGRAM
VCON Oscillator
Amplifier
X+
w/
integrated
varicaps
X-
OE
Q
Q
PL520-20
DIE CONFIGURATION
65 mil
25 24 23 22 21 20 19 18
XIN 26
XOUT 27
Die ID:
A1919-19B
DNC 28
DNC 29
OE 30
VCON 31
C502A
12345 6 78
(1550,1475)
17 GNDBUF
16 CMOS
15 LVDSB
14 PECLB
13 VDDBUF
12 VDDBUF
11 PECL
10 LVDS
9 OE_SELECT
Y (0,0)
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
OUTPUT SELECTION AND ENABLE
Pad #18
OUTSEL1
0
0
1
1
Pad #25
OUTSEL0
0
1
0
1
Selected Output
High Drive CMOS
Standard CMOS
L VD S
PECL (default)
OE_SELECT
(Pad #9)
OE
(Pad #30)
State
0
0 Tri-state
1 (Default) Output enabled
1 (Default)
0 (Default) Output enabled
1 Tri-state
Pad #9, 18, 25 : Bond to GND to se t to “0 ”, bond to VD D to se t to “1 ”
No connec tion resul ts to “de fau l t” se tting through in ternal pu ll -up/-do wn.
Pad #30: Logical s ta tes de fined by PECL leve ls i f O E_SELECT (pad #9) is “1 ”
Logical s ta tes de fined by CM OS levels i f O E_SELECT is “0 ”
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 3/13/07 Page 1
PL520-20 pdf, 반도체, 판매, 대치품
PL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
5. Jitter Specifications
PARAMETERS
Period Jitter RMS at 155MHz *
Period Jitter peak-to-peak at 155MHz *
Accumulated Jitter RMS at 155MHz *
Accumulated Jitter peak-to-peak, 155MHz *
Random Jitter *
Integrated jitter RMS at 155MHz
* Measured on Wavecrest SIA 3000 at VDD=3.3V
CONDITIONS
At 155.52MHz, wit h capacitive
decoupling between VDD and GND.
Over 10,000 cycles
At 155.52MHz, with capacitive
decoupling between VDD and GND.
Over 1,000,000 cycles.
Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5
18.5
2.5
24
2.5
0.3
MAX. UNITS
ps
20
ps
27
ps
0.4 ps
6. Phase Noise Specifications
PARAMETERS
FREQUENCY
Phase Noise relative to
carrier
155.52MHz
Note: Phase Noise measured at VCON = 0V, VDD=3.3V
@10Hz
-75
@100Hz @1kHz @10kHz @100kHz UNITS
-95 -125 -140 -145 dBc/Hz
7. CMOS Electrical Specifications
3.3V Supplies
PARAMETERS
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
SYMBOL
IOH
IOL
IOH
IOL
CONDITIONS
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
MIN.
30
30
10
10
TYP. MAX.
2.4
1.2
UNITS
mA
mA
mA
mA
ns
2.5V Supplies
PARAMETERS
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
SYMBOL
IOH
IOL
IOH
IOL
CONDITIONS
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
0.25V ~ 2.25V with 15 pF
lo ad
0.25V ~ 2.25V with 15 pF
lo ad
MIN. TYP. MAX. UNITS
20 mA
20 mA
6.5 mA
6.5 mA
3.0
ns
1.5
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 3/13/07 Page 4

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PL520-20 전자부품, 판매, 대치품
PL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
PAD ASSIGNMENT
Pad #
Name
X (m)
Y (m)
1 GND 248 109
2 GND 361 109
3 GND 473 109
4 GND 587 109
5 GND 702 109
6
DNC (Do Not Connect)
874
109
7 GND 1042 109
8
GNDBUF
1171 109
9
OE_SELECT
1400 125
10
LVDS
1400 259
11
PECL
1400 476
12
VDDBUF
1400 616
13
VDDBUF
1400 716
14
PECLB
1400 871
15
LVDSB
1400 1089
16
CMOS
1400 1227
17
GNDBUF
1389 1365
18
OUTSEL1
1232 1365
19
DNC (Do Not Connect)
1042
1365
20
DNC (Do Not Connect)
854
1365
21 VDD 659 1365
22 VDD 559 1365
23 VDD 459 1365
24 VDD 358 1365
25
OUTSEL0
194 1365
26 XIN 109 1223
27
XOUT
109 1017
28
DNC (Do Not Connect)
109
858
29
DNC (Do Not Connect)
109
646
30 OE 109 397
31
VCON
109 181
Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 3/13/07 Page 7

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PL520-20

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