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PL685-28 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 PL685-28
기능 19MHz to 250MHz Low Phase-Noise XO
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PL685-28 데이터시트, 핀배열, 회로
(Preliminary) PL685-28
FE AT UR E S
19MHz to 250MHz Low Phase-Noise XO
PAD CONFIGURATION
< 0.6ps RMS phase jitter (12kHz to 20MHz) at
155.52MHz
30ps max peak to peak period jitter
8bit Switch Capacitor for ±50PPM crystal CLoad
tuning
о Load Capacitance Tuning Range: 8pF to 12pF
Ultra Low-Power Consumption
о < 90 mA @155MHz PECL output
о <10A at Power Down (PDB) Mode
Input Frequency:
о Fundamental Crystal: 19MHz to 40MHz
Output Frequency:
о 19MHz to 250MHz output.
Output types: LVPECL.
Programmable OE input polarity selection.
Power Supply: 3.3V, ±10%
Operating Temperature Ranges:
о Commercial: 0C to 70C
о Industrial: -40C to 85C
Available in Die or Wafer
DESCRIPTION
The PL685-28 is a Dual LC core monolithic IC clock,
capable of maintaining sub-1ps RMS phase jitter,
while covering a wide frequency output range up to
250MHz, without the use of external components.
The high performance and high frequency output is
achieved using a low cost fundamental crystal of
between 19MHz and 40 MHz. The PL685-28 is
designed to address the demanding requirements of
high performance applications such as Fiber
Channel, serial ATA, Ethernet, SAN, SONET/SDH,
etc.
65 mil
SCLK 9
8
Die ID
OE/PDB/
SDIO
DNC
10
11
GND_ANA
GND_DIG
GND_BUF
12
13
14
(0,0)
PL685
(1650,2250)
7
6 VDD_ANA
5 VDD_DIG
4 VDD_BUF
3 QB
2 VDD_BUF
1Q
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
65 x 88.6 mil
GND
80 micron x 80 micron
8 mils
OUTPUT ENABLE CONTROL
OE Select
(Programmable)
OE
State
0
0 (Default)
1
Output enabled
Tri-state
1 (Default)
0
1 (Default)
Tri-state
Output enabled
BLOCK DIAGRAM
OE/PDB
XIN/REF
XOUT
Xtal
Osc
(Default pre-programmed output path)
PD/CP
LF HF
LCVCOs
Pre-scalar
4/6
/2
Programmable Function
M Divider
(5 bit)
P Divider
(4 bit)
/2
Q
QB
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/02/11 Page 1




PL685-28 pdf, 반도체, 판매, 대치품
(Preliminary) PL685-28
ELECTRICAL SPECIFICATIONS
19MHz to 250MHz Low Phase-Noise XO
1. ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL MIN MAX UNITS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature (industrial temperature)*
Ambient Operating Temperature (commercial temperature)
Junction Temperature
ESD Protection, Machine Model
VDD
VI
VO
TS
TAI
TAC
TJ
4.6 V
-0.5
VDD+0.5
V
-0.5
VDD+0.5
V
-65 150 C
-40 85 C
0 70 C
125 C
200 V
ESD Protection, Human Body Model
2 kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permane nt damage to the
device and affect product reliability. These co nditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to
commercial grade only.
2. GENERAL ELECTRICAL SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Supply Current, Dynamic
Supply Current, Dynamic
PDB Enabled
Output Enable Time
IDDQ LVPECL, 155.52MHz, 3.3V
PDB = 0, 3.3V
OE logic 0 to logic 1, Ta=25º C.
tOE
Add one clock period to this
measurement for a usable clock
output.
90 mA
10 uA
50 ns
Power Up Time
TPU PDB logic 0 to logic 1, Ta=25º C
10 ms
Operating Voltage
Power Up Ramp Rate
Auto-Calibration Time
Output Clock Duty Cycle
VDD
2.97 3.3 3.63
V
tPU
Time for VDD to reach 90% VDD.
Power ramp must be monotonic.
0.1
100 ms
tAC At power up
10 ms
@ VDD 1.3V
45 50 55 %
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/02/11 Page 4

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PL685-28

19MHz to 250MHz Low Phase-Noise XO

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