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PDF ST10F269Z2T3 Data sheet ( Hoja de datos )
| Número de pieza | ST10F269Z2T3 | |
| Descripción | 16-BIT MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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ST10F269Zx
16-BIT MCU WITH MAC UNIT,
128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM
DATASHEET
■ HIGH PERFORMANCE 32 OR 40 MHZ CPU WITH
DSP FUNCTION
– 16-bit CPU With 4-stage Pipeline
– 50ns (or 62.5ns) Instruction Cycle Time at 40MHz (or
32MHz) Max CPU Clock
– Multiply/accumulate Unit (Mac) 16 X 16-bit Multipli-
cation, 40-bit Accumulator
– Repeat Unit
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operat-
ing Systems
– Single-cycle Context Switching Support
■ MEMORY ORGANIZATION
– 128K or 256K Byte On-chip Flash Memory Single Volt-
age With Erase/program Controller
– Up to 1K Erasing/programming Cycles
– Up to 16 MByte Linear Address Space For Code And
Data (5 MBytes With CAN)
– 2K Byte On-chip Internal RAM (IRAM)
– 10K Byte On-chip Extension RAM (XRAM)
■ FAST AND FLEXIBLE BUS
– Programmable External Bus Characteristics for Dif-
ferent Address Ranges
– 8-bit or 16-bit External Data Bus
– Multiplexed or Demultiplexed External Address/data
Buses
– Five Programmable Chip-select Signals
– Hold-acknowledge Bus Arbitration Support
■ INTERRUPT
– 8-channel Peripheral Event Controller for Single Cy-
cle Interrupt Driven Data Transfer
– 16-priority-level Interrupt System with 56 Sources,
Sampling Rate Down to 25ns at 40MHz (31.25ns at
32MHz)
■ TIMERS
– Two Multi-functional General Purpose Timer Units
with 5 Timers
■ TWO 16-CHANNEL CAPTURE / COMPARE UNITS
■ A/D CONVERTER
– 16-channel 10-bit
– 4.85µs Conversion Time at 40MHz CPU Clock
(6.06µs at 32MHz)
■ 4-CHANNEL PWM UNIT
■ SERIAL CHANNELS
– Synchronous / Asynchronous Serial Channel
– High-speed Synchronous Channel
PQFP144 (28 x 28 mm) (Plastic Quad Flat Pack)
TQFP144 (20 x 20 x 1.40 mm) (Thin Quad Flat Pack)
■ TWO CAN 2.0B INTERFACES OPERATING ON
ONE OR TWO CAN BUSSES (30 OR 2x15
MESSAGE OBJECTS)
■ FAIL-SAFE PROTECTION
– Programmable Watchdog Timer
– Oscillator Watchdog
■ ON-CHIP BOOTSTRAP LOADER
■ CLOCK GENERATION
– On-chip PLL
– Direct or Prescaled Clock Input
■ REAL TIME CLOCK
■ UP TO 111 GENERAL PURPOSE I/O LINES
– Individually Programmable as Input, Output or Spe-
cial Function
– Programmable Threshold (Hysteresis)
■ IDLE AND POWER DOWN MODES
■ SINGLE VOLTAGE SUPPLY: 5V ±10% (EMBEDDED
REGULATOR FOR 2.7 or 3.3 V CORE SUPPLY).
■ TEMPERATURE RANGES: -40 +125°C / -40 to 85°C
■ 144-PIN PQFP/TQFP PACKAGES
128K or 256KByte
Flash Memory
32
CPU-Core and MAC Unit
16
16
2K Byte
Internal
RAM
10K Byte
XRAM
CAN1_RXD
CAN1_TXD
CAN2_RXD
CAN2_TXD
CAN1
CAN2
16 Watchdog
PEC
Oscillator
and PLL
Interrupt Controller
XTAL1 XTAL2
16
3.3V Voltage
Regulator
16
16
8
Port 6
8
Por t 5
16
BRG
BRG
Port 3
15
Port 7
8
16
Port 8
8
September 2003
1/184
1 page  
ST10F269
TABLE OF CONTENTS
PAGE
21.4.7 - Phase Locked Loop ..................................................................................... 149
21.4.8 - External Clock Drive XTAL1 ........................................................................ 150
21.4.9 - Memory Cycle Variables ............................................................................. 151
21.4.10 - Multiplexed Bus ........................................................................................... 152
21.4.11 - Demultiplexed Bus ...................................................................................... 160
21.4.12 - CLKOUT and READY ................................................................................. 168
21.4.13 - External Bus Arbitration ............................................................................... 171
21.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing ............................ 174
21.4.14.1Master Mode ................................................................................ 174
21.4.14.2Slave mode .................................................................................. 175
22 - Package Mechanical Data ..................................................................................... 178
23 - Ordering Information ............................................................................................... 180
ERRATA SHEET
1 - DESCRIPTION ....................................................................................................... 181
2 - FUNCTIONAL PROBLEMS .................................................................................... 181
2.1 - PWRDN.1 - EXECUTION OF PWRDN INSTRUCTION ............................................. 181
2.2 - MAC.9 - COCMP INSTRUCTION INVERTED OPERANDS ....................................... 182
2.3 - MAC.10 - E FLAG EVALUATION FOR COSHR AND COASHR INSTRUCTIONS WHEN
SATURATION MODE IS ENABLED ........................................................................... 182
2.4 - ST_PORT.3 - BAD BEHAVIOR OF HYSTERESIS FUNCTION ON INPUT FALLING
EDGE .......................................................................................................................... 183
3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICATION ............................ 183
4 - ERRATA SHEET VERSION INFORMATION ......................................................... 183
5/184
5 Page 
ST10F269
2 - PIN DATA
Symbol
Pin Type
Function
P0L.0 - P0L.7, 100-107, I/O Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or
P0H.0
108,
output via direction bit. Programming an I/O pin as input forces the corresponding
P0H.1 - P0H.7 111-117
output driver to high impedance state.
In case of an external bus configuration, PORT0 serves as the address (A) and as
the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in
demultiplexed bus modes.
Demultiplexed bus modes
Data Path Width:
P0L.0 – P0L.7:
P0H.0 – P0H.7
8-bit
D0 – D7
I/O
Multiplexed bus modes
16-bit
D0 - D7
D8 - D15
Data Path Width: 8-bit
16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7 A8 – A15 AD8 - AD15
P1L.0 - P1L.7 118-125
P1H.0 - P1H.7 128-135
I/O Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. PORT1 is used as the 16-bit address bus (A)
in demultiplexed bus modes and also after switching from a demultiplexed bus mode
to a multiplexed bus mode.
The following PORT1 pins have alternate functions:
132 I P1H.4 CC24IO
CAPCOM2: CC24 Capture Input
133 I P1H.5 CC25IO
CAPCOM2: CC25 Capture Input
134 I P1H.6 CC26IO
CAPCOM2: CC26 Capture Input
135 I P1H.7 CC27IO
CAPCOM2: CC27 Capture Input
XTAL1
138 I XTAL1 Oscillator amplifier and/or external clock input.
XTAL2
137 O XTAL2 Oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in the
AC Characteristics must be observed.
RSTIN
140 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified
duration while the oscillator is running resets the ST10F269. An internal pull-up
resistor permits power-on reset using only a capacitor connected to VSS. In bidirec-
tional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the
RSTIN line is pulled low for the duration of the internal reset sequence.
RSTOUT
141 O Internal Reset Indication Output. This pin is driven to a low level during hardware,
software or watchdog timer reset. RSTOUT remains low until the EINIT (end of ini-
tialization) instruction is executed.
NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to
vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the
PWRDN (power down) instruction is executed, the NMI pin must be low in order to
force the ST10F269 to go into power down mode. If NMI is high and PWDCFG =’0’,
when PWRDN is executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
VAREF
37 - A/D converter reference voltage.
VAGND
38 - A/D converter reference ground.
RPD
84 - Timing pin for the return from interruptible powerdown mode and synchronous /
asynchronous reset selection.
11/184
11 Page | ||
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