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Si7445DP PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 Si7445DP
기능 P-Channel 20-V (D-S) MOSFET
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Si7445DP 데이터시트, 핀배열, 회로
P-Channel 20-V (D-S) MOSFET
Si7445DP
Vishay Siliconix
PRODUCT SUMMARY
VDS (V)
RDS(on) (Ω)
0.0077 at VGS = - 4.5 V
- 20 0.0094 at VGS = - 2.5 V
0.0125 at VGS = - 1.8 V
PowerPAK SO-8
ID (A)
- 19
- 17
- 15
FEATURES
Halogen-free According to IEC 61249-2-21
Available
• TrenchFET® Power MOSFET
• New Low Thermal Resistance PowerPAK®
Package with Low 1.07 mm Profile
• 100 % Rg Tested
APPLICATIONS
• Load Switch Battery Applications
6.15 mm
D
8D
7
D
6
D
5
S
1S
5.15 mm
2
S
3
G
4
Bottom View
Ordering Information: Si7445DP-T1-E3 (Lead (Pb)-free)
Si7445DP-T1-GE3 (Lead (Pb)-free and Halogen-free)
S
G
D
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
10 s Steady State
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150°C)a
Pulsed Drain Current
Continuous Source Current (Diode Conduction)a
Maximum Power Dissipationa
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)b, c
TA = 25°C
TA = 70°C
TA = 25°C
TA = 70°C
VDS
VGS
ID
IDM
IS
PD
TJ, Tstg
- 20
±8
- 19 - 12
- 15 - 9
- 50
- 4.3
- 1.6
5.4 1.9
3.4 1.2
- 55 to 150
260
Unit
V
A
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambienta
t 10 s
Steady State
RthJA
18
52
23
65 °C/W
Maximum Junction-to-Case (Drain)
Steady State
RthJC
1.0
1.3
Notes
a. Surface Mounted on 1" x 1" FR4 board.
b. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 71626
S09-0270-Rev. D, 16-Feb-09
www.vishay.com
1




Si7445DP pdf, 반도체, 판매, 대치품
Si7445DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.6
ID = 250 µA
0.4
200
160
0.2 120
0.0 80
- 0.2 40
- 0.4
- 50 - 25
0 25 50 75 100 125 150
TJ - Temperature (°C)
Threshold Voltage
2
1
Duty Cycle = 0.5
0
0.001
0.01
0.1
1
10
Time (s)
Single Pulse Power, Junction-to-Ambient
0.2
0.1
0.1
0.05
0.02
0.01
10 - 4
Single Pulse
10 - 3
2
Notes:
PDM
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = R thJA = 65 °C/W
3. T JM - TA = PDMZthJA(t)
4. Surface Mounted
10 - 2
10 - 1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
100
600
1
Duty Cycle = 0.5
0.2
0.1
0.1 0.05
0.02
Single Pulse
0.01
10 - 4
10 - 3
10 - 2
10 - 1
Square Wave Pulse Duration (s)
1
Normalized Thermal Transient Impedance, Junction-to-Case
10
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, seem www.vishay.com/ppg?71626.
www.vishay.com
4
Document Number: 71626
S09-0270-Rev. D, 16-Feb-09

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Si7445DP 전자부품, 판매, 대치품
www.vishay.com
Application Note AN821
Vishay Siliconix
PowerPAK® SO-8 Mounting and Thermal Considerations
PowerPAK SO-8 DUAL
The pin arrangement (drain, source, gate pins) and the pin
dimensions of the PowerPAK SO-8 dual are the same as
standard SO-8 dual devices. Therefore, the PowerPAK
device connection pads match directly to those of the SO-8.
As in the single-channel package, the only exception is the
extended drain connection area. Manufacturers can likewise
take immediate advantage of the PowerPAK SO-8 dual
devices by mounting them to existing SO-8 dual land
patterns.
To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended land
pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click on the
PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the
PowerPAK SO-8 dual package.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder
reflow as a test preconditioning and are then
reliability-tested using temperature cycle, bias humidity,
HAST, or pressure pot. The solder reflow temperature profile
used, and the temperatures and time duration, are shown in
figures 3 and 4.
For the lead (Pb)-free solder profile, see
www.vishay.com/doc?73257.
Fig. 3 Solder Reflow Temperature Profile
Ramp-Up Rate
Temperature at 150 - 200 °C
Temperature Above 217 °C
Maximum Temperature
Time at Maximum
Temperature
Ramp-Down Rate
+ 3 °C /s max.
120 s max.
60 - 150 s
255 + 5/- 0 °C
30 s
+ 6 °C/s max.
150 - 200 °C
260 °C
3 °C(max)
30 s
217 °C
60 s (min.)
Pre-Heating Zone
150 s (max.)
Reflow Zone
Maximum peak temperature at 240 °C is allowed.
6 °C/s (max.)
Fig. 4 Solder Reflow Temperatures and Time Durations
Revision: 16-Mai-13
2 Document Number: 71622
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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P-Channel 20-V (D-S) MOSFET

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