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MTB1306 데이터시트 PDF




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부품번호 MTB1306 기능
기능 Power MOSFET ( Transistor )
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MTB1306 데이터시트, 핀배열, 회로
MTB1306
Preferred Device
Power MOSFET
75 Amps, 30 Volts, Logic Level
N−Channel D2PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Avalanche Energy Specified
Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured − Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 1.0 M)
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tp 10 ms)
Drain Current
− Continuous
− Continuous @ 100°C
− Single Pulse (tp 10 µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C
(Note 1.)
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
30 Vdc
30 Vdc
± 20 Vdc
± 20 Vpk
75 Adc
59
225 Apk
150 Watts
1.2 W/°C
2.5 Watts
Operating and Storage Temperature
Range
TJ, Tstg
−55 to
150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak
IL = 75 Apk, L = 0.1 mH, RG = 25 )
EAS
mJ
280
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 1.)
RθJC
RθJA
RθJA
°C/W
0.8
62.5
50
Maximum Lead Temperature for Soldering
Purposes, 1/8from Case for 5.0
seconds
TL
260 °C
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
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75 AMPERES
30 VOLTS
RDS(on) = 6.5 m
N−Channel
D
G
S
12
3
4
D2PAK
CASE 418B
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
MTB1306
YWW
12
Gate Drain
3
Source
MTB1306
Y
WW
= Device Code
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
MTB1306
MTB1306T4
D2PAK
D2PAK
50 Units/Rail
800/Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2000
September, 2004 − Rev.XXX
1
Publication Order Number:
MTB1306/D




MTB1306 pdf, 반도체, 판매, 대치품
MTB1306
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
9000
VDS = 0 V
8000
Ciss
7000
VGS = 0 V
6000
5000 Crss
4000
3000
Ciss
2000
1000
0
−10
Coss
Crss
−5.0 0 5.0
VGS VDS
10
15 20
25
VGS OR VDS, GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTB1306 전자부품, 판매, 대치품
MTB1306
Standard Cell Density
trr
High Cell Density
trr
ta
tb
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
1000
VGS = 10 V
SINGLE PULSE
TC = 25°C
100
10
1.0 ms
10 ms
dc
1.0
0.1
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1.0 10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
280
240 ID = 75 A
200
160
120
80
40
0
25 50
75 100 125
TJ, STARTING JUNCTION TEMPERATURE (°C)
150
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
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