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LV8824QA PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 LV8824QA
기능 PWM Driver IC
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LV8824QA 데이터시트, 핀배열, 회로
Ordering number : ENA2083
LV8824QA
Bi-CMOS IC
For Brushless Motor Drive
PWM Driver IC
http://onsemi.com
Overview
The LV8824QA is a PWM pre-driver IC suitable for use in 3-phase brushless motors. This IC was designed based on
the assumption that Nch FETs are used as the upper and lower output transistors. The rotational speed is controllable by
inputting PWM pulse or DC voltage externally and changing duty. LV8824QA incorporates latch-type constraint
protection circuit.
Features
IO max = 50mA
Speed control and synchronous rectification by PWM direct input (3.3V input-ready) and DC voltage.
3-Hall FG output
Latch type constraint protection circuit (latch is released by S/B and F/R.)
Forward/reverse switch circuit, Hall bias pin
Power saving circuit
Current limiter circuit, Low-voltage protection circuit, Thermal shut-down circuit
Charge pump circuit (external Nch/Nch), 5V regulator output.
Start/Brake circuit
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
Output current
Allowable power dissipation
VCC max
VG max
IO max
Pd max
VCC pin
VG pin
Mounted on a circuit board.*1
34
42
50
1.45
V
V
mA
W
Junction temperature
Tj max
150 °C
Operating temperature
Topr
-40 to +105 °C
Storage temperature
Tstg
-55 to +150 °C
*1 : Specified circuit board : 100mm × 100mm × 1.6mm, glass epoxy (double-layer board)
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
May, 2013
70412 SY 20120626-S00007 No.A2083-1/13




LV8824QA pdf, 반도체, 판매, 대치품
Package Dimensions
unit : mm (typ)
3436
TOP VIEW
5.0
SIDE VIEW
BOTTOM VIEW
(3.5)
LV8824QA
2
1.5
1.45
12
SIDE VIEW
21
0.25 0.5 (0.75)
1
0.5
Pd max – Ta
Specified board : 100 × 100 × 1.6mm3
glass epoxy(two-layer board)
0.52
SANYO : VQFN32U(5.0X5.0)
0
--40 --20 0 20 40 60 80 100 120
Ambient temperature, Ta -- °C
Pin Assignment
32 31 30 29 28 27 26 25
HB 1
IN3-
IN3+
IN2-
2
3
4
IN2+
IN1-
5
6
IN1+ 7
SGND 8
24 UL
23 UOUT
22 UH
21 VL
20 VOUT
19 VH
18 WL
17 WOUT
9 10 11 12 13 14 15 16
No.A2083-4/13

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LV8824QA 전자부품, 판매, 대치품
Continued from preceding page.
LV8824QA
Pin No.
12
13
Pin Name
CP2
CP1
14 VCC
15 VG
16 WH
19 VH
22 UH
17 WOUT
20 VOUT
23 UOUT
18 WL
21 VL
24 UL
Pin function
Capacitor connect pin for charge pump.
Connect a capacitor between CP1 and
CP2.
Supply pin for control.
Connect a capacitor between this pin
and GND to reject noise.
(See P.12 “14. Supply stabilization”)
Charge pump output pin.
(Power supply for upper FET gate.)
Connect a capacitor between this pin
and VCC.
(See P.10 “7. Charge pump circuit”)
High side output pin.
(Output pin for gate driver of upper side
Nch power FET.)
(See P.9 “1. Output driving circuit.”)
Voltage detection pin.
(Source voltage detection pin of upper
side Nch power FET.”)
(See P.9 “1. Output driving circuit.”)
Low side output pin.
(Output pin for gate driver of lower side
Nch power FET.)
Equivalent Circuit
VCC
14
13
CP CG
15
12
VG
16
19
22
VREG
17
20
23
18
21
24
25 RF
Output current detection pin.
Connect a detection resistor (RF)
between this pin and GND.
Current limit value is obtained as follow:
I = VRF / RF (VREF = 0.2Vtyp).
(See P.9 “2. Current limiter circuit”)
VREG
25
26 S/B
28 F/R
29 PWMIN
27 3FG
Start/Brake selector pin.
“High or OPEN”: Short brake.
“Low”: Start
(See P.12 “13. Power saving circuit”)
Selects forward/reverse rotation.
Voltage level becomes High when this
pin is open.
PWM direct input pin.
Output is controllable by the duty of the
input pulse.
When using PWMIN pin, make sure that
CTL pin is set to High level voltage.
(See P.9 “3. Speed control method”)
3 Hall FG signal output pin.
Open drain output.
VREG
26
28
29
VREG
27
Continued on next page.
No.A2083-7/13

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LV8824QA

PWM Driver IC

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