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MMSF10N02Z PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 MMSF10N02Z
기능 Power MOSFET
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MMSF10N02Z 데이터시트, 핀배열, 회로
MMSF10N02Z
Preferred Device
Power MOSFET
10 Amps, 20 Volts
NChannel SO8
EZFETst are an advanced series of Power MOSFETs which
contain monolithic backtoback zener diodes. These zener diodes
provide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature low RDS(on) and true logic
level performance. They are capable of withstanding high energy in
the avalanche and commutation modes and the draintosource diode
has a very low reverse recovery time. EZFET devices are designed for
use in low voltage, high speed switching applications where power
efficiency is important.
Zener Protected Gates Provide Electrostatic Discharge Protection
Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package Saves Board Space
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 MΩ)
GatetoSource Voltage Continuous
Drain Current Continuous @ TA = 25°C
Drain Current Continuous @ TA = 70°C
Drain Current Single Pulse (tp 10 μs)
Total Power Dissipation @ TA = 25°C
(Note 1.)
VDSS
VDGR
VGS
ID
ID
IDM
PD
20 Vdc
20 Vdc
± 12 Vdc
10 Adc
7.0
80 Apk
2.5 Watts
Operating and Storage Temperature Range TJ, Tstg 55 to
150
°C
Thermal Resistance Junction to Ambient
RθJA
50 °C/W
Maximum Temperature for Soldering
TL 260 °C
1. When mounted on 1square FR4 or G10 board (VGS = 4.5 V, @
10 Seconds)
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10 AMPERES
20 VOLTS
RDS(on) = 15 mW
NChannel
D
G
S
MARKING
DIAGRAM
8
SO8
CASE 751
STYLE 12
10N02Z
LYWW
1
L = Location Code
Y = Year
WW = Work Week
PIN ASSIGNMENT
Source
Source
Source
Gate
18
27
36
45
Top View
Drain
Drain
Drain
Drain
ORDERING INFORMATION
Device
Package
Shipping
MMSF10N02ZR2
SO8 2500 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 Rev. 4
1
Publication Order Number:
MMSF10N02Z/D




MMSF10N02Z pdf, 반도체, 판매, 대치품
MMSF10N02Z
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
2000
TJ = 25°C
VGS = 0 V
1500
Ciss
1000
Coss
500 Crss
0
0 2 4 6 8 10 12 14 16 18 20
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MMSF10N02Z 전자부품, 판매, 대치품
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
MMSF10N02Z
TYPICAL ELECTRICAL CHARACTERISTICS
0.001
1.0E−05
SINGLE PULSE
1.0E−04
1.0E−03
1.0E−02
1.0E−01
1.0E+00
t, TIME (s)
Figure 13. Thermal Response
1.0E+01
1.0E+02
1.0E+03
IS
tp
di/dt
trr
ta tb
0.25 IS
IS
TIME
Figure 14. Diode Reverse Recovery Waveform
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