MTD15N06V

Preferred Device

Power MOSFET

15 Amps, 60 Volts

N−Channel DPAK

This Power MOSFET is designed to withstand high energy in the

avalanche and commutation modes. Designed for low voltage, high

speed switching applications in power supplies, converters and power

motor controls, these devices are particularly well suited for bridge

circuits where diode speed and commutating safe operating areas are

critical and offer additional safety margin against unexpected voltage

transients.

• Avalanche Energy Specified

• IDSS and VDS(on) Specified at Elevated Temperature

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating

Symbol Value Unit

Drain−Source Voltage

Drain−Gate Voltage (RGS = 1.0 MΩ)

Gate−Source Voltage

− Continuous

− Single Pulse (tp ≤ 50 ms)

Drain Current − Continuous @ 25°C

Drain Current − Continuous @ 100°C

Drain Current − Single Pulse (tp ≤ 10 μs)

Total Power Dissipation @ 25°C

Derate above 25°C

Total Power Dissipation @ TA = 25°C (Note 2)

Operating and Storage Temperature Range

VDSS

VDGR

VGS

VGSM

ID

ID

IDM

PD

TJ, Tstg

60 Vdc

60 Vdc

± 20

± 25

15

8.7

45

55

0.36

2.1

−55 to

175

Vdc

Vpk

Adc

Apk

Watts

W/°C

Watts

°C

Single Pulse Drain−to−Source Avalanche

Energy − Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc,

IL = 15 Apk, L = 1.0 mH, RG = 25 Ω)

EAS 113 mJ

Thermal Resistance

− Junction to Case

− Junction to Ambient (Note 1)

− Junction to Ambient (Note 2)

RθJC

RθJA

RθJA

°C/W

2.73

100

71.4

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds

TL 260 °C

1. When surface mounted to an FR4 board using the minimum recommended

pad size.

2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size.

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V(BR)DSS

60 V

RDS(on) TYP

80 mW

ID MAX

15 A

N−Channel

D

G

4

12

3

DPAK

CASE 369C

Style 2

4

S

MARKING DIAGRAMS

4

Drain

1

Gate

2

Drain

3

Source

4

Drain

1 23

DPAK

CASE 369D

Style 2

15N06V

Y

WW

Device Code

= Year

= Work Week

12 3

Gate Drain Source

ORDERING INFORMATION

Device

Package

Shipping

MTD15N06V

MTD15N06V−1

MTD15N06VT4

DPAK

DPAK

Straight Lead

DPAK

75 Units/Rail

75 Units/Rail

2500 Tape &

Reel

© Semiconductor Components Industries, LLC, 2006

August, 2006 − Rev. 5

1

Publication Order Number:

MTD15N06V/D

MTD15N06V

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge

controlled. The lengths of various switching intervals (Δt)

are determined by how fast the FET input capacitance can

be charged by current from the generator.

The published capacitance data is difficult to use for

calculating rise and fall because drain−gate capacitance

varies greatly with applied voltage. Accordingly, gate

charge data is used. In most cases, a satisfactory estimate of

average input current (IG(AV)) can be made from a

rudimentary analysis of the drive circuit so that

t = Q/IG(AV)

During the rise and fall time interval when switching a

resistive load, VGS remains virtually constant at a level

known as the plateau voltage, VSGP. Therefore, rise and fall

times may be approximated by the following:

tr = Q2 x RG/(VGG − VGSP)

tf = Q2 x RG/VGSP

where

VGG = the gate drive voltage, which varies from zero to VGG

RG = the gate drive resistance

and Q2 and VGSP are read from the gate charge curve.

During the turn−on and turn−off delay times, gate current is

not constant. The simplest calculation uses appropriate

values from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG − VGSP)]

td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at

a voltage corresponding to the off−state condition when

calculating td(on) and is read at a voltage corresponding to the

on−state when calculating td(off).

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET

source lead, inside the package and in the circuit wiring

which is common to both the drain and gate current paths,

produces a voltage at the source which reduces the gate drive

current. The voltage is determined by Ldi/dt, but since di/dt

is a function of drain current, the mathematical solution is

complex. The MOSFET output capacitance also

complicates the mathematics. And finally, MOSFETs have

finite internal gate resistance which effectively adds to the

resistance of the driving source, but the internal resistance

is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate

resistance (Figure 9) shows how typical switching

performance is affected by the parasitic circuit elements. If

the parasitics were not present, the slope of the curves would

maintain a value of unity regardless of the switching speed.

The circuit used to obtain the data is constructed to minimize

common inductance in the drain and gate circuit loops and

is believed readily achievable with board mounted

components. Most power electronic loads are inductive; the

data in the figure is taken with a resistive load, which

approximates an optimally snubbed inductive load. Power

MOSFETs may be safely operated into an inductive load;

however, snubbing reduces switching losses.

1500

VDS = 0 V

1200

Ciss

900

VGS = 0 V

TJ = 25°C

600 Crss

Ciss

300 Coss

Crss

0

10 5 0 5 10 15 20 25

VGS VDS

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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4