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MTD15N06V PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 MTD15N06V
기능 Power MOSFET
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MTD15N06V 데이터시트, 핀배열, 회로
MTD15N06V
Preferred Device
Power MOSFET
15 Amps, 60 Volts
NChannel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
DrainSource Voltage
DrainGate Voltage (RGS = 1.0 MΩ)
GateSource Voltage
Continuous
Single Pulse (tp 50 ms)
Drain Current Continuous @ 25°C
Drain Current Continuous @ 100°C
Drain Current Single Pulse (tp 10 μs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
TJ, Tstg
60 Vdc
60 Vdc
± 20
± 25
15
8.7
45
55
0.36
2.1
55 to
175
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
Single Pulse DraintoSource Avalanche
Energy Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc,
IL = 15 Apk, L = 1.0 mH, RG = 25 Ω)
EAS 113 mJ
Thermal Resistance
Junction to Case
Junction to Ambient (Note 1)
Junction to Ambient (Note 2)
RθJC
RθJA
RθJA
°C/W
2.73
100
71.4
Maximum Lead Temperature for Soldering
Purposes, 1/8from case for 10 seconds
TL 260 °C
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size.
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V(BR)DSS
60 V
RDS(on) TYP
80 mW
ID MAX
15 A
NChannel
D
G
4
12
3
DPAK
CASE 369C
Style 2
4
S
MARKING DIAGRAMS
4
Drain
1
Gate
2
Drain
3
Source
4
Drain
1 23
DPAK
CASE 369D
Style 2
15N06V
Y
WW
Device Code
= Year
= Work Week
12 3
Gate Drain Source
ORDERING INFORMATION
Device
Package
Shipping
MTD15N06V
MTD15N06V1
MTD15N06VT4
DPAK
DPAK
Straight Lead
DPAK
75 Units/Rail
75 Units/Rail
2500 Tape &
Reel
© Semiconductor Components Industries, LLC, 2006
August, 2006 Rev. 5
1
Publication Order Number:
MTD15N06V/D




MTD15N06V pdf, 반도체, 판매, 대치품
MTD15N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
1500
VDS = 0 V
1200
Ciss
900
VGS = 0 V
TJ = 25°C
600 Crss
Ciss
300 Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTD15N06V 전자부품, 판매, 대치품
MTD15N06V
PACKAGE DIMENSIONS
B
VR
DPAK
CASE 369C01
ISSUE O
T
SEATING
PLANE
C
E
S
F
4
1 23
A
K
J
LH
D 2 PL
G 0.13 (0.005) M T
U
Z
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.101
3.0
0.118
5.80
0.228
1.6
0.063
6.172
0.243
INCHES
DIM MIN MAX
A 0.235 0.245
B 0.250 0.265
C 0.086 0.094
D 0.027 0.035
E 0.018 0.023
F 0.037 0.045
G 0.180 BSC
H 0.034 0.040
J 0.018 0.023
K 0.102 0.114
L 0.090 BSC
R 0.180 0.215
S 0.025 0.040
U 0.020 −−−
V 0.035 0.050
Z 0.155 −−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERS
MIN MAX
5.97 6.22
6.35 6.73
2.19 2.38
0.69 0.88
0.46 0.58
0.94 1.14
4.58 BSC
0.87 1.01
0.46 0.58
2.60 2.89
2.29 BSC
4.57 5.45
0.63 1.01
0.51 −−−
0.89 1.27
3.93 −−−
ǒ ǓSCALE 3:1
mm
inches
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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