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MTDF1C02HD PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 MTDF1C02HD
기능 Power MOSFET
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MTDF1C02HD 데이터시트, 핀배열, 회로
MTDF1C02HD
Preferred Device
Power MOSFET
1 Amp, 20 Volts
Complementary Micro8t
These Power MOSFET devices are capable of withstanding high
energy in the avalanche and commutation modes and the draintosource
diode has a very low reverse recovery time. Micro8 devices are designed
for use in low voltage, high speed switching applications where power
efficiency is important. Typical applications are dcdc converters, and
power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be used
for low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
Miniature Micro8 Surface Mount Package Saves Board Space
Extremely Low Profile (<1.1mm) for thin applications such as
PCMCIA cards
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery
Life
Logic Level Gate Drive Can Be Driven by Logic ICs
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for Micro8 Package Provided
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Negative sign for PChannel devices omitted for clarity
Rating
Symbol Max
DraintoSource Voltage
NChannel
PChannel
VDSS
20
20
DraintoGate Voltage (RGS = 1.0 MW)
NChannel
PChannel
VDGR
20
20
GatetoSource Voltage Continuous
NChannel
PChannel
VGS
±8.0
±8.0
Operating and Storage Temperature Range
TJ and
Tstg
55 to
150
Unit
V
V
V
°C
http://onsemi.com
1 AMPERE, 20 VOLTS
RDS(on) = 120 mW (NChannel)
1 AMPERE, 20 VOLTS
RDS(on) = 175 mW (PChannel)
7
D
NChannel
8
5
D
PChannel
6
2
G
1S
4
G
3S
MARKING
DIAGRAM
8
Micro8
CASE 846A
WW
STYLE 2
CA
1
WW = Date Code
PIN ASSIGNMENT
Source1
Gate1
Source2
Gate2
18
27
36
45
Top View
Drain1
Drain1
Drain2
Drain2
ORDERING INFORMATION
Device
Package
Shipping
MTDF1C02HDR2 Micro8 4000 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 Rev. 2
1
Publication Order Number:
MTDF1C02HD/D




MTDF1C02HD pdf, 반도체, 판매, 대치품
MTDF1C02HD
ELECTRICAL CHARACTERISTICS continued (TA = 25°C unless otherwise noted) (Note 2)
Characteristic
Symbol Polarity Min
SWITCHING CHARACTERISTICS continued (Note 4)
Total Gate Charge
GateSource Charge
GateDrain Charge
(VDS = 16 Vdc, ID = 1.7 Adc,
VGS = 4.5 Vdc) (Note 2)
(VDS = 16 Vdc, ID = 1.2 Adc,
VGS = 4.5 Vdc) (Note 2)
QT
Q1
Q2
Q3
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
SOURCEDRAIN DIODE CHARACTERISTICS (TC = 25°C)
Forward Voltage (Note 3)
(IS = 1.7 Adc, VGS = 0 Vdc)
(Note 2)
(IS = 1.2 Adc, VGS = 0 Vdc)
Reverse Recovery Time
VSD
trr
(N)
(P)
(N)
(P)
(IF = IS,
dIS/dt = 100 A/μs) (Note 2)
ta
tb
(N)
(P)
(N)
(P)
Reverse Recovery Stored
Charge
QRR
(N)
(P)
2. Negative signs for PChannel device omitted for clarity.
3. Pulse Test: Pulse Width 300 μs, Duty Cycle 2%.
4. Switching characteristics are independent of operating junction temperature.
Typ Max
3.9 5.5
5.3 7.5
0.4
0.7
1.7
2.6
1.5
1.9
0.84
0.89
29
86
14
27
15
59
0.018
0.115
1.0
1.1
Unit
nC
Vdc
ns
μC
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MTDF1C02HD 전자부품, 판매, 대치품
MTDF1C02HD
TYPICAL ELECTRICAL CHARACTERISTICS
1000
VGS = 0 V
100
10
1.0
NChannel
TJ = 125°C
100°C
25°C
0.1
0 5.0 10 15
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. DrainToSource Leakage
Current versus Voltage
20
PChannel
100
TJ = 125°C
10
100°C
1.0
0.1
0
25°C
4.0 8.0 12
VGS = 0 V
16 20
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. DrainToSource Leakage
Current versus Voltage
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
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MTDF1C02HD

Power MOSFET

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