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M75N06HD PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 M75N06HD
기능 Power MOSFET
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M75N06HD 데이터시트, 핀배열, 회로
MTP75N06HD
Preferred Device
Power MOSFET
75 A, 60 V, N−Channel, TO−220
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low−voltage, high−speed switching applications in power supplies,
converters and PWM motor controls, and inductive loads. The
avalanche energy capability is specified to eliminate the guesswork in
designs where inductive loads are switched, and to offer additional
safety margin against unexpected voltage transients.
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Avalanche Energy Specified
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−Source Voltage
Drain−Gate Voltage (RGS = 1.0 MW)
Gate−Source Voltage − Continuous
Gate−Source Voltage − Single Pulse
VDSS
VDGR
VGS
60
60
± 20
± 30
Vdc
Vdc
Vdc
Vpk
Drain Current − Continuous
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (tp 10 ms)
Total Power Dissipation
Derate above 25°C
ID 75 Adc
ID 50
IDM 225 Apk
PD 150 W
1.0 W/°C
Operating and Storage Temperature
Range
TJ, Tstg
−55 to
175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc,
IL = 75 Apk, L = 0.177 mH, RG = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
EAS
RqJC
RqJA
500 mJ
°C/W
1.0
62.5
Maximum Lead Temperature for Soldering
Purposes, 1/8from case for 10
seconds
TL
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
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75 AMPERES
60 VOLTS
RDS(on) = 10 mW
N−Channel
D
G
S
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
4
TO−220AB
CASE 221A
STYLE 5
M75N06HD
LLYWW
1
2
3
M75N06HD
LL
Y
WW
1
Gate
3
Source
2
Drain
= Device Code
= Location Code
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
MTP75N06HD TO−220AB
50 Units/Rail
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2004
June, 2004 − Rev. 3
1
Publication Order Number:
MTP75N06HD/D




M75N06HD pdf, 반도체, 판매, 대치품
MTP75N06HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
7000
VDS = 0 V
6000
Ciss
5000
VGS = 0 V
TJ = 25°C
4000
3000 Crss
Ciss
2000
1000
0
10
5 05
VGS VDS
Coss
Crss
10 15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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M75N06HD 전자부품, 판매, 대치품
MTP75N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
1.0
D = 0.5
0.2
0.1
0.1 0.05
0.02
0.01
0.01
1.0E−05
SINGLE PULSE
1.0E−04
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
Figure 14. Thermal Response
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E+00
1.0E+01
IS
tp
di/dt
trr
ta tb
0.25 IS
IS
TIME
Figure 15. Diode Reverse Recovery Waveform
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M75N06HD

Power MOSFET

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