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부품번호 HUFA76504DK8 기능
기능 Logic Level UltraFET Power MOSFET
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HUFA76504DK8 데이터시트, 핀배열, 회로
Data Sheet
HUFA76504DK8
June 2001
[ /Title
(HUF7
6400S
K8)
/Sub-
ject
(60V,
0.072
Ohm,
4A, N-
Chan-
nel,
Logic
Level
UltraFE
2.3A, 80V, 0.222 Ohm, Dual N-Channel,
Logic Level UltraFET Power MOSFET
Packaging
JEDEC MS-012AA
BRANDING DASH
1
2
3
4
5
Symbol
SOURCE1 (1)
GATE1 (2)
DRAIN 1 (8)
DRAIN 1 (7)
Power
MOS-
FET)
/Author
SOURCE2 (3)
GATE2 (4)
DRAIN 2 (6)
DRAIN 2 (5)
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.200Ω, VGS = 10V
- rDS(ON) = 0.222Ω, VGS = 5V
• Simulation Models
- Temperature Compensated PSPICE™ and SABER
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.Fairchildsemi.com
• Internal RG = 50
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Transient Thermal Impedance Curve vs Board Mounting
Area
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUFA76504DK8
MS-012AA
76504DK8
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUFA76504DK8T.
/Key-
words
(Harris
Semi-
conduc-
tor, N-
Chan-
nel,
Logic
Level
UltraFE
Power
MOS-
Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified
HUFA76504DK8
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous
Continuous
Continuous
Continuous
(TA=
(TA=
(TA=
(TA=
1122005500ooCCooCC,, ,,VVVVGGGGSSSS====15450V.VV)5))(VN(()NFo(itogFetuieg2rue)3r)2e. )..2(..)N..(oN.. t..oe..te2.. )..3...)
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ID
ID
ID
ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
80
80
±16
2.3
2.5
1.1
1.1
Figure 4
Figures 6, 17, 18
V
V
V
A
A
A
A
Power Dissipation (Note 2)
Derate Above 25oC . . . .
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PD
...
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
NOTES:
1. TJ = 25oC to 125oC.
2. 50oC/W measured using FR-4 board with 0.76 in2 (490.3 mm2) copper pad at 1 second.
3. 228oC/W measured using FR-4 board with 0.006 in2 (3.87 mm2) copper pad at 1000 seconds.
2.5
20
-55 to 150
300
260
W
mW/oC
oC
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.mtp.intersil.com/automotive.html.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET® is a registered trademark of Fairchild Corporation. PSPICE® is a registered trademark of Cadence Corporation.
SABER© is a registered trademark of Avanti corporation.




HUFA76504DK8 pdf, 반도체, 판매, 대치품
HUFA76504DK8
Typical Performance Curves (Continued)
200
SINGLE PULSE
100
TJ
TA
=
=
MAX RATED
25oC
10
100µs
OPERATION IN THIS
1
AREA MAY BE
LIMITED BY rDS(ON)
1ms
0.1
1
RθJA = 228oC/W
10ms
10 100
VDS, DRAIN TO SOURCE VOLTAGE (V)
200
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
20
ItfASRVTA==R(0LT)I(NIAGST)/J(1=.31*R50AoTCED BVDSS - VDD)
If R 0
10 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
1
0.01
0.1
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
1
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
8 VDD = 15V
6
4
TJ = 25oC
2
TJ = 150oC
TJ = -55oC
0
2.0
2.5 3.0 3.5 4.0
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
4.5
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
8 TA = 25oC
VGS = 4.5V
6
VGS = 10V
4
2
VGS = 3.5V
VGS = 3V
0
012
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 8. SATURATION CHARACTERISTICS
3
350
300
ID = 2.5A
250
ID = 1.1A
200
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
VGS = 10V, ID = 2.5A
1.5
1.0
150
2
468
VGS, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
©2001 Fairchild Semiconductor Corporation
0.5
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Rev. A, June 4, 2001

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HUFA76504DK8 전자부품, 판매, 대치품
HUFA76504DK8
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in
an application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
PDM
=
(---T----J---M-------–----T----A-----)
RθJA
(EQ. 1)
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 23
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 23 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a cofficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
RθJA = 103.2 24.3 × ln (Area)
(EQ. 2)
300
RθJA = 103.2 - 24.3 * ln(AREA)
250 228 oC/W - 0.006in2
200 191 oC/W - 0.027in2
150
100
50
Rθβ = 46.4 - 21.7 * ln(AREA)
0
0.001
0.01
0.1
AREA, TOP COPPER AREA (in2) PER DIE
1
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
While Equation 2 describes the thermal resistance of a
single die, several of the new UltraFET™s are offered with
two die in the SOP-8 package. The dual die SOP-8 package
introduces an additional thermal component, thermal
coupling resistance, Rθβ. Equation 3 describes Rθβ as a
function of the top copper mounting pad area.
Rθβ = 46.4 21.7 × ln (Area)
(EQ. 3)
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 23. It is important to note the
t(hReθrβm) aalrereesqisutaivnacleen(tRfθoJrAb)oathndditeh.eFrmorael xcaomupplilnegarte0s.1istsaqnucaere
inches of copper:
RθJA1 = RθJA2 = 159°C/W
Rθβ1 = Rθβ2 = 97°C/W
TJ1 and TJ2 define the junction temerature of the respective
die. Similarly, P1 and P2 define the power dissipated in each
die. The steady state junction temperature can be calculated
using Equation 4 for die 1and Equation 5 for die 2.
Example: To calculate the junction temperature of each die
when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0
Watts. The ambient temperature is 70°C and the package is
mounted to a top copper area of 0.1 square inches per die.
Use Equation 4 to calulate TJ1 and and Equation 5 to
calulate TJ2.
.
TJ1 = P1RθJA + P2Rθβ + TA
(EQ. 4)
TJ1 = (0 Watts)(159°C/W) + (0.5 Watts)(97°C/W) + 70°C
TJ1 = 119°C
TJ2 = P2RθJA + P1Rθβ + TA
(EQ. 5)
TJ2 = (0.5 Watts)(159°C/W) + (0 Watts)(97°C/W) + 70°C
TJ2 = 150°C
©2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001

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부품번호상세설명 및 기능제조사
HUFA76504DK8

Logic Level UltraFET Power MOSFET

Fairchild Semiconductor
Fairchild Semiconductor

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