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PDF NB3L8533 Data sheet ( Hoja de datos )
| Número de pieza | NB3L8533 | |
| Descripción | 2.5V/3.3V Differential 2:1 MUX to 4 LVPECL Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
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NB3L8533
2.5V/3.3V Differential 2:1
MUX to 4 LVPECL Fanout
Buffer
Description
The NB3L8533 is a low skew 1:4 LVPECL Clock fanout buffer
designed explicitly for low output skew applications.
The NB3L8533 features a multiplexed input which can be driven by
either a differential or single−ended input to allow for the distribution
of a lower speed clock along with the high speed system clock.
The CLK_SEL pin will select the differential clock inputs, CLK and
CLK, when LOW (or left open and pulled LOW by the internal
pull−down resistor). When CLK_SEL is HIGH, the Differential
PCLK and PCLK inputs are selected.
The common enable (CLK_EN) is synchronous so that the outputs
will only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore, all associated specification limits are referenced to
the negative edge of the clock input.
Features
• 650 MHz Maximum Clock Output Frequency
• CLK/CLK can Accept LVPECL, LVDS, HCSL, STTL and HSTL
• PCLK/PCLK can Accept LVPECL, LVDS, CML and SSTL
• Four Differential LVPECL Clock Outputs
• 1.5 ns Maximum Propagation Delay
• Operating Range: VCC = 2.375 V to 3.630 V
• LVCMOS Compatible Control Inputs
• Selectable Differential Clock Inputs
• Synchronous Clock Enable
• 30 ps Max. Skew Between Outputs
• −40°C to +85°C Ambient Operating Temperature Range
• TSSOP−20 Package
• These are Pb−Free Devices
Applications
• Computing and Telecom
• Routers, Servers and Switches
• Backplanes
www.onsemi.com
MARKING
DIAGRAM
TSSOP−20
DT SUFFIX
CASE 948E
NB3L
8533
ALYW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
+
CLK_EN
D
Q
CLK
CLK
+
PCLK
PCLK
+
CLK_SEL
0
1
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Simplified Logic Diagram of
NB3L8533
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 1
1
Publication Order Number:
NB3L8533/D
1 page  
NB3L8533
Table 6. AC CHARACTERISTICS, VCC = 2.375 V to 3.630 V, TA = −40°C to +85°C (Note 9)
Symbol
Characteristic
Min Typ Max Unit
fMAX
FN
Maximum Input Clock Frequency: VOUTpp ≥ 300 mV
Phase Noise, fC = 156.25 MHz
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
Offset from Carrier
650 MHz
−124.4
−136.1
−144.2
−153.3
−156.2
−156.2
−156.4
dBc/
Hz
tPLH,
tPHL
t∫FN
Propagation Delay to Differential Outputs, @ 50 MHz
(Figures 6 and 7) (VCC = 3.3 V)
Additive Phase Jitter, RMS; fC = 156.25 MHz,
Integration Range: 12 kHz − 20 MHz
Note 10
Note 11
CLK/CLK to Q/Q
PCLK/PCLK to Q/Q
1.0
1.55 ns
0.05 ps
tsk(o) Output−to−output skew; (Note 12)
30 ps
tsk (pp) Part−to−Part Skew; (Note 13)
150 ps
VINpp
tr/tf
ODC
Input Voltage Swing/Sensitivity (Differential Configuration) (Note 15)
Output rise and fall times, 20% to 80%, @ 50 MHz
Output Clock Duty Cycle
Qn, Qn
150
250
47
1300
600
53
mV
ps
%
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the
declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device
specification limit values are applied individually under normal operating conditions and not valid simultaneously.
All parameters measured at fMAX unless noted otherwise.
The cycle−to−cycle jitter on the input will equal the jitter on the output. The part does not add jitter
9. Measured using a VINPPmin source, Reference Duty Cycle = 50% duty cycle clock source. All output loading with external 50 W to VCC − 2 V.
10. Measured from the differential input crossing point to the differential output crossing point.
11. Measured from VCC /2 input crossing point to the differential output crossing point.
12. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross
points.
13. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the
same type of inputs on each device, the outputs are measured at the differential cross points.
14. Output voltage swing is a single−ended measurement operating in differential mode.
15. Input voltage swing is a single−ended measurement operating in differential mode.
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