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MTB36N06V 데이터시트 PDF




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기능 Power MOSFET ( Transistor )
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MTB36N06V 데이터시트, 핀배열, 회로
MTB36N06V
Preferred Device
Power MOSFET
32 Amps, 60 Volts
NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
DraintoSource Voltage
DraintoGate Voltage (RGS = 1.0 MΩ)
GatetoSource Voltage
Continuous
NonRepetitive (tp 50 μs)
Drain Current Continuous @ 25°C
Drain Current Continuous @ 100°C
Drain Current Single Pulse (tp 10 μs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C
(Note 1.)
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60 Vdc
60 Vdc
± 20
± 25
32
22.6
112
90
0.6
3.0
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
Operating and Storage Temperature
Range
TJ, Tstg
55 to
175
°C
Single Pulse DraintoSource Avalanche
Energy Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak
IL = 32 Apk, L = 0.1 mH, RG = 25 Ω)
EAS
205 mJ
Thermal Resistance
Junction to Case
Junction to Ambient
Junction to Ambient (Note 1.)
RθJC
RθJA
RθJA
°C/W
1.67
62.5
50
Maximum Lead Temperature for Soldering
Purposes, 1/8from Case for 10
seconds
TL
260 °C
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
http://onsemi.com
32 AMPERES
60 VOLTS
RDS(on) = 40 mΩ
NChannel
D
G
S
12
3
4
D2PAK
CASE 418B
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
MTB36N06V
YWW
12
Gate Drain
3
Source
MTB36N06V
Y
WW
= Device Code
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
MTB36N06V
MTB36N06VT4
D2PAK
D2PAK
50 Units/Rail
800/Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 Rev. 4
1
Publication Order Number:
MTB36N06V/D




MTB36N06V pdf, 반도체, 판매, 대치품
MTB36N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
4000
VDS = 0 V VGS = 0 V
TJ = 25°C
3000 Ciss
2000
Crss Ciss
1000
Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTB36N06V 전자부품, 판매, 대치품
MTB36N06V
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.33
8.38
0.42
10.66
0.63
17.02
0.08
2.032
0.04
1.016
0.24
6.096
0.12
3.05
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a
surface mount device is determined by TJ(max), the
maximum rated junction temperature of the die, RθJA, the
thermal resistance from the device junction to ambient, and
the operating temperature, TA. Using the values provided
on the data sheet, PD can be calculated as follows:
PD =
TJ(max) TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device. For a
D2PAK device, PD is calculated as follows.
PD =
175°C 25°C = 3.0 Watts
50°C/W
The 50°C/W for the D2PAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 3.0 Watts. There are
other alternatives to achieving higher power dissipation
from the surface mount packages. One is to increase the
area of the drain pad. By increasing the area of the drain
pad, the power dissipation can be increased. Although one
can almost double the power dissipation with this method,
one will be giving up area on the printed circuit board
which can defeat the purpose of using surface mount
technology. For example, a graph of RθJA versus drain pad
area is shown in Figure 16.
70
Board Material = 0.0625
G−10/FR−4, 2 oz Copper TA = 25°C
60
2.5 Watts
50
3.5 Watts
40
5 Watts
30
20
0 2 4 6 8 10 12 14 16
A, AREA (SQUARE INCHES)
Figure 16. Thermal Resistance versus Drain Pad
Area for the D2PAK Package (Typical)
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