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기능 Power MOSFET ( Transistor )
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MTB50N06V 데이터시트, 핀배열, 회로
MTB50N06V
Preferred Device
Power MOSFET
42 Amps, 60 Volts
NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
DrainSource Voltage
DrainGate Voltage (RGS = 1.0 MΩ)
GateSource Voltage
Continuous
NonRepetitive (tp 10 ms)
Drain Current Continuous @ 25°C
Drain Current Continuous @ 100°C
Drain Current Single Pulse (tp 10 μs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C
(Note 1)
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60 Vdc
60 Vdc
± 20
± 25
42
30
147
125
0.83
3.0
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
Operating and Storage Temperature
Range
TJ, Tstg
55 to
175
°C
Single Pulse DraintoSource Avalanche
Energy Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc,
IL = 42 Apk, L = 0.454 μH, RG = 25 Ω)
EAS
400 mJ
Thermal Resistance
JunctiontoCase
JunctiontoAmbient
JunctiontoAmbient (Note 1)
RθJC
RθJA
RθJA
°C/W
1.2
62.5
50
Maximum Lead Temperature for Soldering
Purposes, 1/8from case for 10 sec
TL
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
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42 AMPERES
60 VOLTS
RDS(on) = 28 mΩ
NChannel
D
G
12
3
S
4
D2PAK
CASE 418B
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
MTB50N06V
AYWW
12
Gate Drain
3
Source
A = Assembly Location
Y = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MTB50N06V
MTB50N06VT4
D2PAK
D2PAK
50 Units/Rail
800/Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 Rev. 5
1
Publication Order Number:
MTB50N06V/D




MTB50N06V pdf, 반도체, 판매, 대치품
MTB50N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
6000
VDS = 0 V
5000 Ciss
VGS = 0 V
TJ = 25°C
4000
3000 Crss
2000
Ciss
1000
0
10
Crss
50 5
VGS VDS
Coss
10 15 20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4

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MTB50N06V 전자부품, 판매, 대치품
MTB50N06V
PACKAGE DIMENSIONS
D2PAK
CASE 418B04
ISSUE J
B
4
C
E
V
W
123
S
T
SEATING
PLANE
G
K
D 3 PL
0.13 (0.005) M T B M
A
W
J
H
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B01 THRU 418B03 OBSOLETE,
NEW STANDARD 418B04.
INCHES
DIM MIN MAX
A 0.340 0.380
B 0.380 0.405
C 0.160 0.190
D 0.020 0.035
E 0.045 0.055
F 0.310 0.350
G 0.100 BSC
H 0.080 0.110
J 0.018 0.025
K 0.090 0.110
L 0.052 0.072
M 0.280 0.320
N 0.197 REF
P 0.079 REF
R 0.039 REF
S 0.575 0.625
V 0.045 0.055
MILLIMETERS
MIN MAX
8.64 9.65
9.65 10.29
4.06 4.83
0.51 0.89
1.14 1.40
7.87 8.89
2.54 BSC
2.03 2.79
0.46 0.64
2.29 2.79
1.32 1.83
7.11 8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14 1.40
SOLDERING FOOTPRINT*
8.38
0.33
10.66
0.42
17.02
0.67
1.016
0.04
5.08
0.20
3.05
0.12
ǒ ǓSCALE 3:1
mm
inches
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your local
Sales Representative
MTB50N06V/D

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