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MTB75N05HD 데이터시트 PDF




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부품번호 MTB75N05HD 기능
기능 Power MOSFET ( Transistor )
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MTB75N05HD 데이터시트, 핀배열, 회로
MTB75N05HD
Preferred Device
Power MOSFET
75 Amps, 50 Volts
NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a draintosource diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
w These devices are available in Pbfree package(s). Specifications herein
apply to both standard and Pbfree devices. Please see our website at
www.onsemi.com for specific Pbfree orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value
DraintoSource Voltage
VDSS
50
DraintoGate Voltage (RGS = 1.0 MΩ)
VDGR
50
GatetoSource Voltage Continuous
VGS
± 20
Drain Current Continuous
ID 75
Drain Current Continuous @ 100°C
ID 65
Drain Current Single Pulse (tp 10 μs) IDM 225
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C
(minimum footprint, FR4 board)
PD 125
1.0
2.5
Operating and Storage Temperature
Range
TJ, Tstg
55 to
150
Single Pulse DraintoSource Avalanche
Energy Starting TJ = 25°C
(VDD = 25 V, VGS = 10 V, Peak
IL = 75 A, L = 0.177 mH, RG = 25 Ω)
Thermal Resistance
Junction to Case
Junction to Ambient
Junction to Ambient (minimum foot-
print, FR4 board)
EAS
RθJC
RθJA
RθJA
500
1.0
62.5
50
Maximum Temperature for Soldering
Purposes, 1/8from case for 10 s
TL 260
Unit
Volts
Amps
Watts
W/°C
Watts
°C
mJ
°C/W
°C
http://onsemi.com
75 AMPERES
50 VOLTS
RDS(on) = 9.5 mΩ
NChannel
D
G
S
12
3
4
D2PAK
CASE 418B
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
MTB75N05HD
YWW
12
Gate Drain
3
Source
MTB75N05HD = Device Code
Y = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MTB75N05HD
MTB75N05HDT4
D2PAK
D2PAK
50 Units/Rail
800/Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 Rev. 7
1
Publication Order Number:
MTB75N05HD/D




MTB75N05HD pdf, 반도체, 판매, 대치품
MTB75N05HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in a RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with boardmounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
8000 VDS = 0
7000
6000 Ciss
VGS = 0
TJ = 25°C
5000
4000
3000 Crss
2000
Ciss
Coss
1000
Crss
0
10 5 0 5 10 15 20 25
VGS VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTB75N05HD 전자부품, 판매, 대치품
MTB75N05HD
3
2.5
2.0
1.5
1
0.5
0
25
RθJA = 50°C/W
Board material = 0.065 mil FR4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size 450 mils x 350 mils
50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
Figure 15. D2PAK Power Derating Curve
150
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