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MTD20P06HDL 데이터시트 PDF




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기능 Power MOSFET ( Transistor )
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MTD20P06HDL 데이터시트, 핀배열, 회로
MTD20P06HDL
Preferred Device
Power MOSFET
20 Amps, 60 Volts, Logic
Level
P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low−voltage, high−speed switching applications in power supplies,
converters and PWM motor controls, and other inductive loads. The
avalanche energy capability is specified to eliminate the guesswork in
designs where inductive loads are switched, and to offer additional
safety margin against unexpected voltage transients.
Features
Ultra Low RDS(on), High−Cell Density, HDTMOS
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Avalanche Energy Specified
Pb−Free Package is Available
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−Source Voltage
Drain−Gate Voltage (RGS = 1.0 MW)
Gate−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms)
Drain Current
− Continuous
− Continuous @ 100°C
− Single Pulse (tpv10 ms)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C (Note 2)
Operating and Storage Temperature Range
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
TJ, Tstg
60 Vdc
60 Vdc
"15
"20
Vdc
Vpk
15 Adc
9.0
45 Apk
72 W
0.58 W/°C
1.75 W
−55 to
150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc,
IL = 15 Apk, L = 2.7 mH, RG = 25 W)
EAS 300 mJ
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
RqJC
RqJA
RqJA
°C/W
1.73
100
71.4
Maximum Lead Temperature for Soldering
Purposes, 1/8from case for 10 seconds
TL 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using 0.5 sq. inch pad size.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
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20 AMPERES, 60 VOLTS
RDS(on) = 175 mW
P−Channel
D
G
S
MARKING DIAGRAM & PIN ASSIGNMENTS
4 Gate 1
YWW
12
3
DPAK
CASE 369C
Drain 2
20P
06HLG
Source 3
(Surface Mount)
STYLE 2
4
Drain
20P06HL
Y
WW
G
= Device Code
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package Shipping
MTD20P06HDL
DPAK
75 Units/Rail
MTD20P06HDLT4 DPAK 2500 Tape & Reel
MTD20P06HDLT4G DPAK 2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MTD20P06HDL/D




MTD20P06HDL pdf, 반도체, 판매, 대치품
MTD20P06HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
2500
VDS = 0 V
Ciss
2000
VGS = 0 V
TJ = 25°C
1500
Crss
1000
Ciss
500
0
10
Crss
5 05
VGS VDS
10
Coss
15 20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (Volts)
Figure 7. Capacitance Variation
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MTD20P06HDL 전자부품, 판매, 대치품
MTD20P06HDL
TYPICAL ELECTRICAL CHARACTERISTICS
1.0
D = 0.5
0.2
0.1
0.1 0.05
0.02
0.01
1.0E−05
0.01
SINGLE PULSE
1.0E−04
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
Figure 14. Thermal Response
1.0E+00
1.0E+01
IS
tp
di/dt
trr
ta tb
0.25 IS
IS
TIME
Figure 15. Diode Reverse Recovery Waveform
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