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64F2646 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 64F2646
기능 HD64F2646
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64F2646 데이터시트, 핀배열, 회로
Hitachi 16-Bit Single-Chip Microcomputer
H8S/2646 Series
H8S/2646
HD6432646
H8S/2645
HD6432645
H8S/2647
HD6432647
H8S/2648
HD6432648
H8S/2646R F-ZTAT™
HD64F2646R
H8S/2648R F-ZTAT™
HD64F2648R
Hardware Manual
ADE-602-207C
Rev. 4.0
9/20/02
Hitachi, Ltd.
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.




64F2646 pdf, 반도체, 판매, 대치품

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64F2646 전자부품, 판매, 대치품
List of Items Revised or Added for This Version
Section
Page Description
2.10.2 Caution to
observe when using
bit manipulation
instructions
76, 77 Newly added
The BSET, BCLR, BNOT, BST and BIST instructions read data in a unit of byte,
then, after bit manipulation, they write data in a unit of byte. Therefore, caution
must be exercised when executing any of these instructions for registers and
ports that include write-only bits.
The BCLR instruction can be used to clear the flag of an internal I/O register to
0. In that case, if it is clearly known that the pertinent flag is set to 1 in an
interrupt processing routine or other processing, there is no need to read the
flag in advance.
8.3.10 Number of 207
DTC Execution States
4th line changed as follows
Number of execution states = I · (SI +1) + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM,
normal mode is set, and data is transferred from the on-chip ROM to an internal
I/O register, the time required for the DTC operation is 14 states. The time from
activation to the end of the data write is 11 states.
9.4.2 Register
Configuration
Table 9-6 Port 3
Register
Configuration
242
Name
Port 3 data direction register
Port 3 data register
Port 3 register
Port 3 open drain control register
Abbreviation
P3DDR
P3DR
PORT3
P3ODR
R/W
W
R/W
R
R/W
Initial Value
H'00
H'00
Undefined
H'00
Address*
H'FE32
H'FF02
H'FFB2
H'FE46
9.9.2 Register
Configuration
263
9.10.3 Pin Functions 269
Table 9-20 Port C
Pin Functions
9.13.1 Overview
281
Figure 9-12 Port F
Pin Functions
15th line changed as follows
In mode 7, if a pin is in the input state in accordance with the settings in the
DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up
for that pin.
(Incorrect)PCDDR
(Correct)PCnDDR
Pin functions in modes 4 to 6
PF7 (input) / ø (output)
PF6 (I/O) / AS (output) / SEG20 (output) / SEG36* (output)
PF5 (I/O) / RD (output) / SEG19 (output) / SEG35* (output)

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64F2646

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