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PDF SC14046B Data sheet ( Hoja de datos )
| Número de pieza | SC14046B | |
| Descripción | Phase Locked Loop | |
| Fabricantes | ON Semiconductor | |
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SC14046B
Phase Locked Loop
The SC14046B phase locked loop contains two phase comparators,
a voltage−controlled oscillator (VCO), source follower, and zener
diode. The comparators have two common signal inputs, PCAin and
PCBin. Input PCAin can be used directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small voltage
signals. The self−bias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator 1 (an exclusive OR gate)
provides a digital error signal PC1out, and maintains 90° phase shift at
the center frequency between PCAin and PCBin signals (both at 50%
duty cycle). Phase comparator 2 (with leading edge sensing logic)
provides digital error signals, PC2out and LD, and maintains a 0°
phase shift between PCAin and PCBin signals (duty cycle is
immaterial). The linear VCO produces an output signal VCOout
whose frequency is determined by the voltage of input VCOin and the
capacitor and resistors connected to pins C1A, C1B, R1, and R2. The
source−follower output SFout with an external resistor is used where
the VCOin signal is needed but no loading can be tolerated. The inhibit
input Inh, when high, disables the VCO and source follower to
minimize standby power consumption. The zener diode can be used to
assist in power supply regulation.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage−to−frequency conversion and motor speed control.
Features
• Buffered Outputs Compatible with MHTL and Low−Power TTL
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 to 18 V
• Pin−for−Pin Replacement for CD4046B
• Phase Comparator 1 is an Exclusive OR Gate and is Duty Cycle Limited
• Phase Comparator 2 Switches on Rising Edges and is not Duty Cycle
Limited
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD DC Supply Voltage Range
Vin Input Voltage Range (All Inputs)
Iin DC Input Current, per Pin
PD Power Dissipation, per Package
(Note 1)
−0.5 to +18.0
−0.5 to VDD + 0.5
± 10
500
V
V
mA
mW
TA Operating Temperature Range
−55 to +125
°C
Tstg Storage Temperature Range
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “DW” Packages: – 7.0 mW/_C From 65_C To 125_C
http://onsemi.com
MARKING
DIAGRAM
16
SOIC−16
DW SUFFIX
CASE 751G
14046BG
AWLYYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper op-
eration, Vin and Vout should be constrained to the range
VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused out-
puts must be left open.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 0
1
Publication Order Number:
SC14046B/D
1 page  
Input Stage
X X
PCAin PCBin
PC1out
Input Stage
X X
PCAin PCBin
SC14046B
PHASE COMPARATOR 1
00
11
0
PHASE COMPARATOR 2
01
10
1
00
01 10
11
00
10 01
11
00
01 10
11
PC2out
0
3−State
Output Disconnected
1
LD (Lock Detect)
0
1
0
Refer to Waveforms in Figure 3.
Figure 1. Phase Comparators State Diagrams
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic
Using Phase Comparator 1
Using Phase Comparator 2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNo signal on input PCAin.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPhase angle between PCAin and PCBin.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎLocks on harmonics of center frequency.
VCO in PLL system adjusts to center
frequency (f0).
90° at center frequency (f0), approaching
0_ and 180° at ends of lock range (2fL)
Yes
VCO in PLL system adjusts to minimum
frequency (fmin).
Always 0_ in lock (positive rising edges).
No
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSignal input noise rejection.
High
Low
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎLock frequency range (2fL).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCapture frequency range (2fC).
The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2fL = full VCO frequency range = fmax – fmin.
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDepends on low−pass filter characteristics
(see Figure 3). fC v fL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCenter frequency (f0).
The frequency of VCOout, when VCOin = 1/2 VDD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCO output frequency (f).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNote: These equations are intended to be
a design guide. Since calculated component
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎvalues may be in error by as much as a
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎfactor of 4, laboratory experimentation may
be required for fixed designs. Part to part
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎfrequency variation with identical passive
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎcomponents is typically less than ± 20%.
fmin
=
R2(C1
1
+ 32
pF)
fmax
=
R1(C1
1
+ 32
pF)
+ fmin
Where: 10K v R1 v 1 M
10K v R2 v 1 M
100pF v C1 v .01 mF
(VCO input = VSS)
(VCO input = VDD)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFigure 2. Design Information
fC = fL
http://onsemi.com
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