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PDF STK672-640A-E Data sheet ( Hoja de datos )
| Número de pieza | STK672-640A-E | |
| Descripción | 2-phase Stepping Motor Driver | |
| Fabricantes | ON Semiconductor | |
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Ordering number : ENA1130A
STK672-640A-E
Thick-Film Hybrid IC
2-phase Stepping Motor Driver
http://onsemi.com
Overview
The STK672-640A-E is a hybrid IC for use as a unipolar, 2-phase stepping motor driver with PWM current control.
Applications
• Office photocopiers, printers, etc.
Features
• Built-in overcurrent detection function (output current OFF).
• Built-in overheat detection function (output current OFF).
• If either over-current or overheat detection function is activated, the FAULT signal (active low) is output.
• Built-in power on reset function.
• The motor speed is controlled by the frequency of an external clock signal.
• 2 phase or 1-2 phase excitation switching function.
• Using either or both edges of the clock signal switching function.
• Phase is maintained even when the excitation mode is switched.
• Rotational direction switching function.
• Supports schmitt input for 2.5V high level input.
• Incorporating a current detection resistor (0.089Ω: resistor tolerance ±2%), motor current can be set using two
external resistors.
• The ENABLE pin can be used to cut output current while maintaining the excitation mode.
• With a wide current setting range, power consumption can be reduced during standby.
• No motor sound is generated during hold mode due to external excitation current control.
Semiconductor Components Industries, LLC, 2013
June, 2013
62911HKPC 018-08-0035/71608HKIM No. A1130-1/21
1 page  
Precautions
STK672-640A-E
[GND wiring]
• To reduce noise on the 5V system, be sure to place the GND of C01 in the circuit given above as close as possible to
Pin 2 and Pin 6 of the hybrid IC. Also, to achieve accurate current settings, be sure to connect Vref GND to Pin 18
(S.G) used to set the current and to the point where P.G1 and P.G2 share a connection.
[Input pins]
• If VDD is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to S.G, Pin 18,
and do not apply a voltage greater than or equal to VDD voltage.
• Do not wire by connecting the circuit pattern on the P.C.B side to Pins 7, 8, or 11 on the N.C. shown in the internal
block diagram.
• Apply 2.5V high level input to pins 10, 12, 13, 14, 15, and 17.
• Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 10, 12, 13, 14, 15, and 17
are used as inputs, a 1 to 20kΩ pull-up resistor (to VDD) must be used.
At this time, use a device for the open collector driver that has output current specifications that pull the voltage down
to less than 0.8V at Low level (less than 0.8V at Low level when IOL=5mA).
[Current setting Vref]
• Considering the specifications of the Vref input bias current, IIB, a value of 1kΩ or less is recommended for R02.
If the motor current is temporarily reduced, the circuit given below (STK672-630A-E: IOH>0.2A, STK672-640A-E:
IOH>0.3A) is recommended.
5V 5V
R01
Vref
R3 R02
R01
Vref
R3
R02
• Motor current peak value IOH setting
IOH
0
IOH=(Vref÷4.9) ÷Rs
The value of 4.9 in Equation above represents the Vref voltage as divided by a circuit inside the control IC.
Vref=(R02÷ (R01+R02)) ×5V(or 3.3V)
Rs is an internal current detection resistor value of the hybrid IC.
Rs=0.141Ω when using the STK672-630A-E
Rs=0.089Ω when using the STK672-640A-E
No. A1130-5/21
5 Page 
Usage Notes
STK672-640A-E
1. STK672-630A-E, STK672-640A-E input signal functions and timing
[ENABLE, CLOCK and power on reset, RESETB (Input signal timing when power is first applied)]
The control IC of the driver is equipped with a power on reset function capable of initializing internal IC operations
when power is supplied. A 4V typ setting is used for power on reset. Because the specification for the MOSFET gate
voltage is 5V±5%, conduction of current to output at the time of power on reset adds electromotive stress to the
MOSFET due to lack of gate voltage. To prevent electromotive stress, be sure to set ENABLE=Low while VDD,
which is outside the operating supply voltage, is less than 4.75V.
In addition, if the RESETB terminal is used to initialize output timing, be sure to allow at least 10μs until CLOCK
input.
Control IC power (VDD) rising edge
4V typ
3.8V typ
Control IC power on reset
RESETB signal input
No time specification
ENABLE signal input
CLOCK signal input
At least 10μs
At least 10μs
ENABLE, CLOCK, and RESETB Signals Input Timing
[CLOCK (Phase switching clock)]
• Input frequency: DC to 50kHz
• Minimum pulse width: 10μs
• MODE2=1(High) Signals are read on the rising edge.
• MODE2=0(Low) Signals are read on the rising and falling edges.
[CWB (Motor direction setting)]
The direction of rotation is switched by setting CWB to 1 (high) or 0 (low).
See the timing charts for details on the operation of the outputs.
Note: The state of the CWB input must not be changed during the 6.25μs period before and after the rising edge of the
CLOCK input.
[ENABLE (Forcible on/off control of the A, AB, B, and BB outputs, and hybrid IC internal operation)]
ENABLE=1: Normal operation
ENABLE=0: Outputs A, AB, B, and BB forced to the off state.
If, during the state where CLOCK signal input is provided, the ENABLE pin is set to 0 and then is later
restored to the 1 state, the IC will resume operation with the excitation timing continued from before the
point ENABLE was set to 0.
If sudden stop is applied to the CLOCK signal used for motor rotation, the motor axis may advance beyond the
theoretical position due to inertia. To stop at the theoretical position, the SLOW DOWN setting for gradually slowing
the CLOCK cycle is required.
No. A1130-11/21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet STK672-640A-E.PDF ] | |
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