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PDF FS7145 Data sheet ( Hoja de datos )
| Número de pieza | FS7145 | |
| Descripción | Programmable PhaseLocked Loop Clock Generator | |
| Fabricantes | ON Semiconductor | |
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FS7140, FS7145
Programmable Phase-
Locked Loop Clock
Generator
Description
The FS7140 or FS7145 is a monolithic CMOS clock generator/
regenerator IC designed to minimize cost and component count in a
variety of electronic systems. Via the I2C−bus interface, the
FS7140/45 can be adapted to many clock generation requirements.
The length of the reference and feedback dividers, their fine
granularity and the flexibility of the post divider make the FS7140/45
the most flexible stand−alone PLL clock generator available.
Features
• Extremely Flexible and Low−jitter Phase Locked Loop (PLL)
Frequency Synthesis
• No External Loop Filter Components Needed
• 150 MHz CMOS or 340 MHz PECL Outputs
• Completely Configurable via I2C−bus
• Up to Four FS714x can be Used on a Single I2C−bus
• 3.3 V Operation
• Independent On−chip Crystal Oscillator and External Reference
Input
• Very Low “Cumulative” Jitter
• Pb−Free Packages are Available
Applications
• Precision Frequency Synthesis
• Low−frequency Clock Multiplication
• Video Line−locked Clock Generation
• Laser Beam Printers (FS7145)
http://onsemi.com
SOIC−16
01 SUFFIX
CASE 751BA
SSOP−16
02 SUFFIX
CASE 565AE
PIN CONNECTIONS
1
SCL
CLKN
SDA
ADDR0
VSS
XIN
XOUT
ADDR1
CLKP
VDD
*
REF
VSS
N/C
VDD
IPRG
(Top View)
* FS7140 pin 13 = N/C
* FS7145 pin 13 = SYNC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 7
1
Publication Order Number:
FS7140/D
1 page  
FS7140, FS7145
Table 4. DC ELECTRICAL SPECIFICATIONS (Note 1)
Parameter
Symbol
Conditions/Description
Min Typ Max Units
CLOCK OUTPUTS, CMOS MODE (CLKN, CLKP)
Low−level output sink current
IOL
CLOCK OUTPUTS, PECL MODE (CLKN, CLKP)
VO = 0.4 V
−35 mA
IPRG bias voltage
VIPRG
VIPRG will be clamped to this level
when a resistor is connected from
VDD to IPRG
VDD/3
V
IPRG bias current
Sink current to IPRG current ratio
IIPRG
IIPRG − (VVDD − VIPRG) / RSET
3.5 mA
13
Tristate output current
IZ
−10 10 mA
1. Unless otherwise stated, VDD = 3.3 V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characteriza-
tion data are ± 3s from typical. Negative currents indicate flows out of the device.
Table 5. AC TIMING SPECIFICATIONS (Note 2)
Parameter
Symbol
Conditions/Description
Min Typ Max Units
OVERALL
Output frequency*
fo(max)
CMOS outputs
PECL outputs
0 150 MHz
0 300
VCO frequency*
fVCO
CMOS mode rise time*
tr
CMOS mode fall time*
tf
PECL mode rise time*
tr
PECL mode fall time*
tf
REFERENCE FREQUENCY INPUT (REF)
CL = 7 pF
CL = 7 pF
CL = 7 pF; RL = 65 ohm
CL = 7 pF; RL = 65 ohm
40 400 MHz
1 ns
1 ns
1 ns
1 ns
Input frequency
Reference high time
Reference low time
SYNC CONTROL INPUT (SYNC)
FREF
tREHF
tREFL
80 MHz
3 ns
3 ns
Sync high time
Sync low time
CLOCK OUTPUT (CLKN, CLKP)
tSYNCH
tSYNCL
For orderly CLK stop/start
For orderly CLK stop/start
3
3
TCLK
Duty cycle (CMOS mode)*
Measured at 1.4 V
50 %
Duty cycle (PECL mode)*
Jitter, long term (sy(t))*
Measured at zero crossings of
(VCLKP − VCLKN)
50
tj(LT) For valid programming solutions. Long-term (or cumulative) jitter specified is
RMS position error of any edge compared with an ideal clock generated from
the same reference frequency. It is measured with a time interval analyzer us-
ing a 500 microsecond window, using statistics gathered over 1000 samples.
%
ps
FREF/NREF > 1000 kHz
25 ps
FREF/NREF ^ 500 kHz
50 ps
FREF/NREF ^ 250 kHz
100 ps
FREF/NREF ^ 125 kHz
190 ps
FREF/NREF ^ 62.5 kHz
240 ps
Jitter, period (peak−peak)*
tj(DP)
FREF/NREF ^ 31.5 kHz
40 MHz < VCO frequency < 100 MHz
VCO frequency > 100 MHz
300 ps
75 ps
50 ps
2. Unless otherwise stated, VDD = 3.3 V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization
data are ± 3s from typical.
http://onsemi.com
5
5 Page 
FS7140, FS7145
Programming Information
All register bits are cleared to zero on power−up. All register bits may be read back as written.
Table 7. FS7140 REGISTER MAP
Address
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Byte 7
Reserved
(Bit 63)
Must be set
to “0”
Reserved
(Bit 62)
Must be set
to “0”
Reserved
(Bit 61)
Must be set
to “0”
Reserved
(Bit 60)
Must be set
to “0”
Reserved
(Bit 59)
Must be set
to “0”
Reserved
(Bit 58)
Must be set
to “0”
Reserved
(Bit 57)
Must be set
to “0”
Reserved
(Bit 56)
Must be set
to “0”
Byte 6
Reserved
(Bit 55)
Must be set
to “0”
Reserved
(Bit 54)
Must be set
to “0”
SHUT2
(Bit 53)
0 = Normal
1 = Powered
down
Reserved
(Bit 52)
Must be set
to “0”
Reserved
(Bit 51)
Must be set
to “0”
Reserved
(Bit 50)
Must be set
to “0”
Reserved
(Bit 49)
Must be set
to “0”
Reserved
(Bit 48)
Must be set
to “0”
Byte 5
Reserved
(Bit 47)
Must be set
to “0”
LC
(Bit 46)
Loop filter
cap select
LR[1]
(Bit 45)
LR[0]
(Bit 44)
Loop filter resistor select
Reserved
(Bit 43)
Must be set
to “0”
Reserved
(Bit 42)
Must be set
to “0”
CP[1]
(Bit 41)
CP[0]
(Bit 40)
Charge pump current select
Byte 4
CMOS
(Bit 39)
0 = PECL
1 = CMOS
FBKDSRC
(Bit 38)
0 = VCO
output
1 = Post
divider output
FBKDIV[13]
(Bit 37)
8192
FBKDIV[12]
(Bit 36)
4096
FBKDIV[11]
(Bit 35)
2048
FBKDIV[10]
(Bit 34)
1024
FBKDIV[9]
(Bit 33)
512
FBKDIV[8]
(Bit 32)
256
See the Feedback Divider section for disallowed FBKDIV values
Byte 3
FBKDIV[7]
(Bit 31)
128
FBKDIV[6]
(Bit 30)
64
FBKDIV[5]
(Bit 29)
32
FBKDIV[4]
(Bit 28)
16
FBKDIV[3]
(Bit 27)
8
FBKDIV[2]
(Bit 26)
4
FBKDIV[1]
(Bit 25)
2
FBKDIV[0]
(Bit 24)
1
See the Feedback Divider section for disallowed FBKDIV values
Byte 2
POST2[3]
(Bit 23)
POST2[2]
(Bit 22)
POST2[1]
(Bit 21)
POST2[0]
(Bit 20)
POST1[3]
(Bit 19)
POST1[2]
(Bit 18)
POST1[1]
(Bit 17)
POST1[0]
(Bit 16)
Modulus = N + 1 (N = 0 to 11); See Table 12
Modulus = N + 1 (N = 0 to 11); See Table 12
Byte 1
Byte 0
POST3[1]
(Bit 15)
POST3[0]
(Bit 14)
Modulus = 1, 2, 4 or 8;
See Table 12
REFDIV[7]
(Bit 7)
128
REFDIV[6]
(Bit 6)
64
SHUT1
(Bit 13)
0 = Normal
1 = Powered
down
REFDIV[5]
(Bit 5)
32
REFDSRC
(Bit 12)
0 = Crystal
oscillator
1 = REF pin
REFDIV[4]
(Bit 4)
16
REFDIV[11]
(Bit 11)
2048
REFDIV[10]
(Bit 10)
1024
REFDIV[3]
(Bit 3)
8
REFDIV[2]
(Bit 2)
4
REFDIV[9]
(Bit 9)
512
REFDIV[1]
(Bit 1)
2
REFDIV[8]
(Bit 8)
256
REFDIV[0]
(Bit 0)
1
http://onsemi.com
11
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| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet FS7145.PDF ] | |
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