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NCP4305 데이터시트 PDF




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부품번호 NCP4305 기능
기능 Secondary Side Synchronous Rectification Driver
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NCP4305 데이터시트, 핀배열, 회로
NCP4305
Secondary Side
Synchronous Rectification
Driver for High Efficiency
SMPS Topologies
The NCP4305 is high performance driver tailored to control a
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synchronous rectification MOSFET in switch mode power supplies.
Thanks to its high performance drivers and versatility, it can be used in
MARKING
DIAGRAMS
various topologies such as DCM or CCM flyback, quasi resonant
flyback, forward and half bridge resonant LLC.
The combination of externally adjustable minimum off-time and
on-time blanking periods helps to fight the ringing induced by the PCB
layout and other parasitic elements. A reliable and noise less operation
of the SR system is insured due to the Self Synchronization feature. The
8
1
SOIC−8
D SUFFIX
CASE 751
8
NCP4305x
ALYW G
G
1
NCP4305 also utilizes Kelvin connection of the driver to the MOSFET
to achieve high efficiency operation at full load and utilizes a light load
detection architecture to achieve high efficiency at light load.
1 4305x
The precise turn−off threshold, extremely low turn−off delay time
and high sink current capability of the driver allow the maximum
synchronous rectification MOSFET conduction time and enables
DFN8
MN SUFFIX
CASE 488AF
ALYWG
G
maximum SMPS efficiency. The high accuracy driver and 5 V gate
clamp enables the use of GaN FETs.
Features
Self−Contained Control of Synchronous Rectifier in CCM, DCM and
QR for Flyback, Forward or LLC Applications
Precise True Secondary Zero Current Detection
Typically 12 ns Turn off Delay from Current Sense Input to Driver
Rugged Current Sense Pin (up to 200 V)
WDFN8
MT SUFFIX
CASE 511AT
1
5xMG
G
4305x = Specific Device Code
x = A, B, C, D or Q
A = Assembly Location
Ultrafast Turn−off Trigger Interface/Disable Input (7.5 ns)
Adjustable Minimum ON−Time
Adjustable Minimum OFF-Time with Ringing Detection
Adjustable Maximum ON−Time for CCM Controlling of Primary
QR Controller
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
Improved Robust Self Synchronization Capability
8 A / 4 A Peak Current Sink / Source Drive Capability
Operating Voltage Range up to VCC = 35 V
Automatic Light−load & Disable Mode
ORDERING INFORMATION
See detailed ordering and shipping information on page 49 of
this data sheet.
Adaptive Gate Drive Clamp
GaN Transistor Driving Capability (options A and C)
Low Startup and Disable Current Consumption
Maximum Operation Frequency up to 1 MHz
SOIC-8 and DFN−8 (4x4) and WDFN8 (2x2) Packages
These are Pb−Free Devices
Typical Applications
Notebook Adapters
High Power Density AC/DC Power Supplies (Cell
Phone Chargers)
LCD TVs
All SMPS with High Efficiency Requirements
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 1
1
Publication Order Number:
NCP4305/D




NCP4305 pdf, 반도체, 판매, 대치품
NCP4305
PIN FUNCTION DESCRIPTION
ver. A, B, C, D ver. Q
Pin Name
1 1 VCC
2 2 MIN_TOFF
3 3 MIN_TON
4 4 LLD
5 − TRIG/DIS
6 6 CS
7 7 GND
8 8 DRV
− 5 MAX_TON
Description
Supply voltage pin
Adjust the minimum off time period by connecting resistor to ground.
Adjust the minimum on time period by connecting resistor to ground.
This input modulates the driver clamp level and/or turns the driver off during light load
conditions.
Ultrafast turn−off input that can be used to turn off the SR MOSFET in CCM applica-
tions in order to improve efficiency. Activates disable mode if pulled−up for more than
100 ms.
Current sense pin detects if the current flows through the SR MOSFET and/or its body
diode. Basic turn−off detection threshold is 0 mV. A resistor in series with this pin can
decrease the turn off threshold if needed.
Ground connection for the SR MOSFET driver and VCC decoupling capacitor. Ground
connection for minimum on and off time adjust resistors, LLD and trigger inputs.
GND pin should be wired directly to the SR MOSFET source terminal/soldering point
using Kelvin connection. DFN8 exposed flag should be connected to GND
Driver output for the SR MOSFET
Adjust the maximum on time period by connecting resistor to ground.
MIN_TON
CS
ADJ ELAPSED
Minimum ON time
generator
EN
VDD
100mA
CS_ON
CS
detection
CS_OFF
CS_RESET
MIN_TOFF
RESET
ADJ
Minimum OFF ELAPSED
time generator EN
TRIG/ DISABLE
10 A
Vtrig
DISABLE
Disable detection
&
V DRV clamp
modulation
V_DRV
control
LLD
Control logic
DRIVER
DRV Out DRV
VDD
TRIG
DISABLE
DISABLE VCC managment
UVLO
VCC
Disable detection
GND
Figure 5. Internal Circuit Architecture − NCP4305A, B, C, D
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NCP4305 전자부품, 판매, 대치품
NCP4305
ELECTRICAL CHARACTERISTICS
−40°C TJ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VTRIG/DIS = 0 V; VLLD = 0 V; VCS = −1 to +4 V; fCS =
100 kHz, DCCS = 50%, unless otherwise noted. Typical values are at TJ = +25°C
Parameter
Test Conditions
Symbol
Min Typ Max Unit
SUPPLY SECTION
Current Consumption,
RMIN_TON = RMIN_TOFF = 0 kW
CLOAD = 0 nF, fSW = 500 kHz
CLOAD = 1 nF, fSW = 500 kHz
CLOAD = 10 nF, fSW = 500 kHz
A, C
B, D, Q
A, C
B, D, Q
A, C
B, D, Q
ICC 3.3 4.0 5.6 mA
3.8 4.5 6.0
4.5 6.0 7.5
7.7 9.0 10.7
20 25 30
40 50 60
Current Consumption
No switching, VCS = 0 V, RMIN_TON = RMIN_TOFF
=0k
ICC
1.5 2.0 2.5 mA
Current Consumption below UVLO No switching, VCC = VCCOFF – 0.1 V, VCS = 0 V ICC_UVLO
75 125 mA
Current Consumption in Disable
Mode
VLLD = VCC − 0.1 V, VCS = 0 V
VTRIG = 5 V, VLLD = VCC – 3 V, VCS = 0 V
ICC_DIS
40 55 70 mA
45 65 80
DRIVER OUTPUT
Output Voltage Rise−Time
Output Voltage Fall−Time
Driver Source Resistance
Driver Sink Resistance
Output Peak Source Current
Output Peak Sink Current
Maximum Driver Output Voltage
CLOAD = 10 nF, 10% to 90% VDRVMAX
CLOAD = 10 nF, 90% to 10% VDRVMAX
VCC = 35 V, CLOAD > 1 nF, VLLD = 0 V,
(ver. B, D and Q)
tr 40 55 ns
tf 20 35 ns
RDRV_SOURCE
1.2
W
RDRV_SINK
0.5
W
IDRV_SOURCE
4
A
IDRV_SINK
8
A
VDRVMAX 9.0 9.5 10.5 V
Minimum Driver Output Voltage
VCC = 35 V, CLOAD > 1 nF, VLLD = 0 V, (ver. A, C)
VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. B)
VDRVMIN
4.3 4.7
7.2 7.8
5.5
8.5
VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. C)
4.2 4.7 5.3
VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. A)
3.6 4.0 4.4
VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. D, Q)
3.8 4.0 4.4
Minimum Driver Output Voltage
VLLD = VCC − VLLDREC V
VDRVLLDMIN 0.0 0.4 1.2
CS INPUT
V
V
Total Propagation Delay From CS VCS goes down from 4 to −1 V, tf_CS = 5 ns
to DRV Output On
tPD_ON
35 60 ns
Total Propagation Delay From CS VCS goes up from −1 to 4 V, tr_CS = 5 ns
to DRV Output Off
tPD_OFF
12 23 ns
CS Bias Current
Turn On CS Threshold Voltage
Turn Off CS Threshold Voltage
Turn Off Timer Reset Threshold
Voltage
VCS = −20 mV
Guaranteed by Design
ICS −105
VTH_CS_ON −120
VTH_CS_OFF
−1
VTH_CS_RESET 0.42
−100
−75
0.48
−95
−40
0
0.54
mA
mV
mV
V
CS Leakage Current
TRIGGER DISABLE INPUT
VCS = 200 V
ICS_LEAKAGE
0.4 mA
Minimum Trigger Pulse Duration
VTRIG = 5 V; Shorter pulses may not be
proceeded
tTRIG_PW_MIN
10 ns
Trigger Threshold Voltage
Trigger to DRV Propagation Delay
Trigger Blank Time After DRV
Turn−on Event
VTRIG goes from 0 to 5 V, tr_TRIG = 5 ns
VCS drops below VTH_CS_ON
VTRIG_TH
tPD_TRIG
tTRIG_BLANK
1.95
35
2.02
7.5
50
2.15
12.5
65
V
ns
ns
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