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ESD5102 데이터시트 PDF




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기능 ESD Protection Diodes
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ESD5102 데이터시트, 핀배열, 회로
ESD5102
Product Preview
ESD Protection Diodes
Micro−packaged Diodes for ESD
Protection
The ESD5102 is designed to protect voltage sensitive components
from ESD. Excellent clamping capability, low leakage, and fast
response time provide best in class protection on designs that are
exposed to ESD. Because of its small size, it is suited for use in
smartphone, smart-watch, or many other portable / wearable
applications where board space comes at a premium.
Features
Bi−directional Dual Line ESD Protection
Low Capacitance (5 pF Max, I/O to GND)
Small Body Outline Dimensions: 0.705 x 0.23 mm
Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
Low ESD Clamping Voltage
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range TJ −55 to +125 °C
Storage Temperature Range
Tstg − 55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
TL 260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15 kV
±15 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
www.onsemi.com
MARKING
DIAGRAM
DSN3
CASE 152AW
T
M
T = Specific Device Code
M = Month Code
PIN CONFIGURATION
AND SCHEMATIC
123
ORDERING INFORMATION
Device
Package
Shipping
ESD5102FCT5G
DSN3
(Pb−Free)
10,000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. P3
1
Publication Order Number:
ESD5102/D




ESD5102 pdf, 반도체, 판매, 대치품
ESD5102
IEC 61000−4−2 Spec.
Level
First Peak
Test Volt- Current Current at
age (kV)
(A) 30 ns (A)
1 2 7.5 4
2 4 15 8
3 6 22.5 12
48
30 16
Current at
60 ns (A)
2
4
6
8
IEC61000−4−2 Waveform
Ipeak
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 6. IEC61000−4−2 Spec
tP = 0.7 ns to 1 ns
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 7. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 8 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
L
50 W Coax
Cable
S Attenuator
÷
50 W Coax
Cable
10 MW
IM VM
VC DUT
Oscilloscope
Figure 7. Simplified Schematic of a Typical TLP
System
Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
www.onsemi.com
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