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ESD7554 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 ESD7554은 전자 산업 및 응용 분야에서
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부품번호 ESD7554 기능
기능 4-Channel Low Capacitance Dual-Voltage ESD Protection Array
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ESD7554 데이터시트, 핀배열, 회로
ESD7554
4­Channel Low Capacitance
Dual­Voltage ESD
Protection Array
Features
3 Channels of Low Voltage ESD Protection
1 Channel of High Voltage ESD Protection
Provides ESD Protection to IEC6100042 Level 4:
±8 kV Contact Discharge (Pins 13)
±15 kV Contact Discharge (Pin 4)
Low Channel Input Capacitance
Minimal Capacitance Change with Temperature and Voltage
High Voltage Zener Diode Protects Supply Rail
No Need for External Bypass Capacitors
Each I/O Pin Can Withstand Over 1000 ESD Strikes*
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
8
1
WDFN8
CASE 517BC
MARKING
DIAGRAM
30V MG
1G
30V = Specific Device Code
M = Date Code
G = PbFree Package
PINOUT
5 67 8
ÏÏÏÏÏÏDAPÏÏÏÏÏÏ
4 32 1
Bottom View
(Pins up View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
NOTE: Note: Pins 5, and 6 to 8 are connected to a common
substrate.
Figure 1. Electrical Schematic
*Standard test condition is IEC6100042 level 4 test circuit with each pin subjected to ±8 kV contact discharge for 1000 pulses. Discharges
are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production
test to verify that all of the tested parameters are within spec after the 1000 strikes.
© Semiconductor Components Industries, LLC, 2010
November, 2010 Rev. 0
1
Publication Order Number:
ESD7554/D




ESD7554 pdf, 반도체, 판매, 대치품
ESD7554
PERFORMANCE INFORMATION
Input channel capacitance performance curves for low voltage pins
Figure 3. Typical Variation of CIN vs. VIN
(Low Voltage Inputs, f = 1 MHz, VN = 0 V)
Figure 4. Typical Variation of CIN vs. Temp
(Low Voltage Inputs, f = 1 MHz, VN = 0 V)
http://onsemi.com
4

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ESD7554 전자부품, 판매, 대치품
ESD7554
PACKAGE DIMENSIONS
UDFN8, 1.7x1.35, 0.4P
CASE 517BC01
ISSUE O
D
2X
0.10 C
PIN ONE
REFERENCE
ÉÉÉÉÉÉ2X
0.10 C
TOP VIEW
0.05 C
DETAIL B
A
B
E
A
8X 0.05 C
NOTE 4
A1
SIDE VIEW
EXPOSED Cu
MOLD CMPD
ÇÉÇÉA1 A3
DETAIL B
ALTERNATE
CONSTRUCTIONS
(A3)
L1
L
C
SEATING
PLANE
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.25 mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN MAX
A 0.45 0.55
A1 0.00 0.05
L A3 0.13 REF
b 0.15 0.25
D 1.70 BSC
D2 1.10 1.30
E 1.35 BSC
E2 0.30 0.50
e 0.40 BSC
K 0.15 −−−
L 0.20 0.30
L1 −−− 0.05
DETAIL A
8X L
D2
1
E2
8X K
8
e
e/2
8X b
0.10
0.05
CAB
C NOTE 3
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
PACKAGE
OUTLINE
1.40
8X
0.40
1.55
0.50
8X
0.25
1
0.40 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
N. American Technical Support: 8002829855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81357733850
http://onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
ESD7554/D

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부품번호상세설명 및 기능제조사
ESD7554

4-Channel Low Capacitance Dual-Voltage ESD Protection Array

ON Semiconductor
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