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PDF NLAS5223CL Data sheet ( Hoja de datos )
| Número de pieza | NLAS5223CL | |
| Descripción | Dual SPDT Analog Switch | |
| Fabricantes | ON Semiconductor | |
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NLAS5223C, NLAS5223CL
Ultra-Low 0.35 W
Dual SPDT Analog Switch
The NLAS5223C is an advanced CMOS analog switch fabricated in
Sub−micron silicon gate CMOS technology. The device is a dual
Independent Single Pole Double Throw (SPDT) switch featuring
Ultra−Low RON of 0.35 W, at VCC = 4.3 V.
The part also features guaranteed Break Before Make (BBM)
switching, assuring the switches never short the driver.
Features
• Ultra−Low RON, 0.35 W (typ) at VCC = 4.3 V
• NLAS5223C Interfaces with 2.8 V Chipset
• NLAS5223CL Interfaces with 1.8 V Chipset
• Single Supply Operation from 1.65−4.5 V
• Full 0−VCC Signal Handling Capability
• High Off−Channel Isolation
• Low Standby Current, t50 nA
• Low Distortion
• RON Flatness of 0.15 W
• High Continuous Current Capability
♦ ±320 mA Through Each Switch
• Large Current Clamping Diodes at Analog Inputs
♦ ±100 mA Continuous Current Capability
• Package:
♦ 1.4 x 1.8 x 0.55 mm UQFN10 Pb−Free
• These are Pb−Free Devices
Applications
• Cell Phone Audio Block
• Speaker and Earphone Switching
• Ring−Tone Chip/Amplifier Switching
• Modems
www.onsemi.com
MARKING
DIAGRAM
UQFN10
XXMG
CASE 488AT
G
1
XX = Specific Device Code
M = Date Code/Assembly Location
G = Pb−Free Device
(Note: Microdot may be in either location)
NC2
7
GND
6
IN2 8
5 NC1
COM2 9
NO2 10
4 IN1
3 COM1
12
VCC NO1
FUNCTION TABLE
IN 1, 2
NO 1, 2
NC 1, 2
0
OFF
ON
1 ON OFF
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 2
1
Publication Order Number:
NLAS5223C/D
1 page  
NLAS5223C, NLAS5223CL
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol
Parameter
tON Turn−On Time
tOFF Turn−Off Time
tBBM
Minimum Break−Before−Make
Time
Test Conditions
RL = 50 W, CL = 35 pF
(Figures 3 and 4)
RL = 50 W, CL = 35 pF
(Figures 3 and 4)
VIS = 3.0
RL = 50 W, CL = 35 pF
(Figure 2)
Guaranteed Maximum Limit
25°C
−40°C to +85°C
VCC
VIS
(V) (V) Min Typ* Max Min Max
2.3 − 4.5 1.5
50 60
2.3 − 4.5 1.5
30 40
3.0 1.5 2 15
Unit
ns
ns
ns
CIN Control Pin Input Capacitance
CNO/NC NO, NC Port Capacitance
CCOM COM Port Capacitance When Switch is Enabled
*Typical Characteristics are at 25°C.
Typical @ 25, VCC = 3.6 V
3.5
60
200
pF
pF
pF
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol
Parameter
BW Maximum On−Channel −3 dB
Bandwidth or Minimum
Frequency Response
Condition
VIN centered between VCC and GND
(Figure 5)
VONL Maximum Feed−through On Loss VIN = 0 dBm @ 100 kHz to 50 MHz
VIN centered between VCC and GND (Figure 5)
VISO Off−Channel Isolation
f = 100 kHz; VIS = 1 V RMS; CL = 5.0 pF
VIN centered between VCC and GND (Figure 5)
Q Charge Injection Select Input to VIN = VCC to GND, RIS = 0 W, CL = 1.0 nF
Common I/O
Q = CL x DVOUT (Figure 6)
THD Total Harmonic Distortion
THD + Noise
FIS = 20 Hz to 20 kHz, RL = Rgen = 600 W, CL = 50 pF
VIS = 2.0 V RMS
VCT Channel−to−Channel Crosstalk
f = 100 kHz; VIS = 1.0 V RMS, CL = 5.0 pF, RL = 50 W
VIN centered between VCC and GND (Figure 5)
10. Off−Channel Isolation = 20log10 (VCOM/VNO), VCOM = output, VNO = input to off switch.
VCC
(V)
1.65 − 4.5
1.65 − 4.5
1.65 − 4.5
1.65 − 4.5
3.0
1.65 − 4.5
25°C
Typical
24
−0.06
−68
38
0.08
−70
Unit
MHz
dB
dB
pC
%
dB
www.onsemi.com
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| PDF Descargar | [ Datasheet NLAS5223CL.PDF ] | |
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