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PDF ISLA214P Data sheet ( Hoja de datos )
| Número de pieza | ISLA214P | |
| Descripción | ADC | |
| Fabricantes | Intersil | |
| Logotipo |  |
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14-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA214P
The ISLA214P is a series of low power, high performance
14-bit analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard CMOS
process, the series supports sampling rates of up to 250MSPS.
The ISLA214P is part of a pin-compatible family of 12 to 16-bit
A/Ds with maximum sample rates ranging from 130MSPS to
500MSPS.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters,
such as gain and offset. Digital output data is presented in
selectable LVDS or CMOS formats, and can be configured as
full-width, single data rate (SDR) or half-width, double data
rate (DDR). The ISLA214P is available in a 72-contact QFN
package with an exposed paddle. Operating from a 1.8V
supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
Key Specifications
• SNR @ 250/200/130MSPS
73.0/73.8/74.9dBFS fIN = 30MHz
70.6/71.1/70.9dBFS fIN = 363MHz
• SFDR @ 250/200/130MSPS
82/88/88dBc fIN = 30MHz
78/82/84dBc fIN = 363MHz
• Total Power Consumption = 480mW @ 250MSPS
Features
• Single supply 1.8V operation
• Clock duty cycle stabilizer
• 75fs clock jitter
• 700MHz bandwidth
• Programmable built-in test patterns
• Multi-ADC support
- SPI programmable fine gain and offset control
- Support for multiple ADC synchronization
- Optimized output timing
• Nap and sleep modes
- 200µs sleep wake-up time
• Data output clock
• SDR/DDR LVDS-compatible or LVCMOS outputs
• Selectable clock divider
Applications
• Radar array processing
• Software defined radios
• Broadband communications
• High-performance data acquisition
• Communications test equipment
CLKP
CLKN
CLOCK
MANAGEMENT
CLKOUTP
CLKOUTN
VINP
VINN
VCM
SHA
14-BIT
250 MSPS
ADC
+
–
SPI
CONTROL
DIGITAL
ERROR
CORRECTION
D[13:0]P
D[13:0]N
Pin-Compatible Family
MODEL
ISLA216P25
ISLA216P20
ISLA216P13
ISLA214P50
ISLA214P25
ISLA214P20
ISLA214P13
ISLA212P50
ISLA212P25
ISLA212P20
ISLA212P13
RESOLUTION
16
16
16
14
14
14
14
12
12
12
12
SPEED
(MSPS)
250
200
130
500
250
200
130
500
250
200
130
December 5, 2012
FN7572.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISLA214P
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
CMOS PIN FUNCTION
1, 2, 17, 28, 30, 33, 35,
37, 39, 41, 43, 47, 49,
51, 53, 55, 57, 59, 63
DNC Do Not Connect
6, 13, 19, 20, 21, 70, 71,
72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
Tri-Level Power Control (Nap, Sleep modes)
4 VCM Common Mode Output
8, 9
VINN
Analog Input Negative
10, 11
VINP
Analog Input Positive
15
CLKDIV
Tri-Level Clock Divider Control
16
IPTAT
Temperature Monitor (Output current proportional to absolute
temperature)
18
RESETN
Power On Reset (Active Low)
22, 23
CLKP, CLKN
Clock Input True, Complement
24, 25
CLKDIVRSTP, CLKDIVRSTN Synchronous Clock Divider Reset True, Complement
29 D13 CMOS Bit 13 (MSB) Output
31 D12 CMOS Bit 12 Output
34 D11 CMOS Bit 11 Output
36 D10 CMOS Bit 10 Output
38 D9 CMOS Bit 9 Output
40 D8 CMOS Bit 8 Output
42 D7 CMOS Bit 7 Output
44 D6 CMOS Bit 6 Output
46
RLVDS
LVDS Bias Resistor (connect to OVSS with 1% 10kΩ)
48
CLKOUT
CMOS Clock Output
50 D5 CMOS Bit 5 Output
52 D4 CMOS Bit 4 Output
54 D3 CMOS Bit 3 Output
56 D2 CMOS Bit 2 Output
58 D1 CMOS Bit 1 Output
60 D0 CMOS Bit 0 (LSB) Output
64 OR CMOS Over Range
66 SDO SPI Serial Data Output
67 CSB SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
DDR MODE COMMENTS
NC in DDR Mode
DDR Logical Bits 12, 13
NC in DDR Mode
DDR Logical Bits 10, 11
NC in DDR Mode
DDR Logical Bits 8, 9
NC in DDR Mode
DDR Logical Bits 6, 7
NC in DDR Mode
DDR Logical Bits 4, 5
NC in DDR Mode
DDR Logical Bits 2, 3
NC in DDR Mode
DDR Logical Bits 0, 1
DDR Over Range
5 FN7572.2
December 5, 2012
5 Page 
ISLA214P
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
MAX
TYP (Note 5) UNITS
LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)
Input Common Mode Range
Input Differential Swing (peak to peak, single-ended)
CLKDIVRSTP Input Pull-down Resistance
CLKDIVRSTN Input Pull-up Resistance
LVDS OUTPUTS
VICM
VID
RIpd
RIpu
825 1575 mV
250 450 mV
100 kΩ
100 kΩ
Differential Output Voltage (Note 11)
Output Offset Voltage
Output Rise Time
Output Fall Time
CMOS OUTPUTS
VT 3mA Mode
VOS 3mA Mode
tR
tF
1120
612
1150
240
240
1200
mVP-P
mV
ps
ps
Voltage Output High
VOH IOH = -500µA
OVDD - 0.3 OVDD - 0.1
Voltage Output Low
VOL IOL = 1mA
0.1 0.3
Output Rise Time
tR 1.8
Output Fall Time
tF 1.4
NOTES:
10. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD
depending on desired function.
11. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
V
V
ns
ns
Timing Diagrams
INP
INN
CLKN
CLKP
tA
tCPD
CLKOUTN
CLKOUTP
D[12/10/8/6/4/2/0]N
D[12/10/8/6/4/2/0]P
LATENCY = L CYCLES
tDC
tPD
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
FIGURE 1A. LVDS DDR
EVEN
N-1
ODD
N
EVEN
N
11 FN7572.2
December 5, 2012
11 Page | ||
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| PDF Descargar | [ Datasheet ISLA214P.PDF ] | |
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