Datasheet.kr   

ISLA222S 데이터시트 PDF




Intersil에서 제조한 전자 부품 ISLA222S은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 ISLA222S 자료 제공

부품번호 ISLA222S 기능
기능 High Speed Serial Output ADC
제조업체 Intersil
로고 Intersil 로고


ISLA222S 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

ISLA222S 데이터시트, 핀배열, 회로
DATASHEET
Dual 12-bit, 250/200/125 MSPS JESD204B High Speed
Serial Output ADC
ISLA222S
The ISLA222S is a series of low-power, high-performance,
dual-channel 12-bit, analog-to-digital converters. Designed
with FemtoCharge™ technology on a standard CMOS process,
the series supports sampling rates of up to 250MSPS. The
ISLA222S is part of a pin-compatible family of 12- and 14-bit
dual-channel A/Ds with maximum sample rates ranging from
125MSPS to 250MSPS and shares the same analog core as
Intersil's proven ISLA222P series of ADCs. The family
minimizes power consumption while providing state of the art
dynamic performance, offering an optimal performance vs
power trade-off.
Differentiating the ISLA222S from the ISLA222P is its highly
configurable, JESD204B-compliant, high-speed serial output
link. The link offers data rates up to 4.375Gbps per lane and
multiple packing modes. It can be configured to use one, two,
or three lanes to transmit the conversion data, allowing for
flexibility in the receiver design. The SERDES transmitter also
provides deterministic latency and multi-chip time alignment
support to satisfy an application's complex synchronization
requirements.
A Serial Peripheral Interface (SPI) port allows for extensive
configurability of the JESD204B transmitter including access
to its built-in link and transport layer test patterns. The SPI port
also provides control for numerous additional features
including the fine gain and offset adjustments of the two ADC
cores as well as the programmable clock divider, enabling 2x
and 4x harmonic clocking.
The ISLA222S is available in a space saving 7mmx7mm 48 Ld
QFN package. The package features a thermal pad for
improved thermal performance and is specified over the full
industrial temperature range (-40°C to +85°C).
Features
• JESD204A/B high-speed data interface
- JESD204A compliant
- JESD204B device subclass 0 compliant
- JESD204B device subclass 2 compatible
- Up to 3 JESD204 output lanes running up to 4.375Gbps
- Highly configurable JESD204 transmitter
• Multiple chip time alignment and deterministic latency
support (JESD204B device subclass 2)
• SPI programmable debugging features and test patterns
• 48-pin QFN 7mmx7mm package
Key Specifications
• SNR at 250/200/125MSPS
70.6/71.2/71.7 dBFS fIN = 30MHz
70.3/70.7/70.9 dBFS fIN = 190MHz
• SFDR at 250/200/125MSPS
87/93/95 dBc fIN = 30MHz
84/93/86 dBc fIN = 190MHz
• Total Power Consumption: 989mW at 250MSPS
Applications
• Radar and satellite antenna array processing
• Broadband communications and microwave receivers
• High-performance data acquisition
• Communications test equipment
• High-speed medical imaging
Pin-compatible Family
MODEL
ISLA224S25
ISLA224S20
ISLA224S12
ISLA222S25
ISLA222S20
ISLA222S12
RESOLUTION
14
14
14
12
12
12
SPEED
(MSPS)
250
200
125
250
200
125
FIGURE 1. SERDES DATA EYE AT 4.375Gbps
July 6, 2015
FN8302.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.




ISLA222S pdf, 반도체, 판매, 대치품
ISLA222S
Pin Descriptions
PIN NUMBER
2, 11, 14, 15, 46
12, 20, 47, 48
3, 6, 7, 10
4, 5
8, 9
1
44
16, 17
45
13
26, 29, 32, 35, 37, 38
25, 36, 39
22, 24
21, 23
18, 19
27, 28
30, 31
33, 34
40
41
42
43
PAD
NAME
AVDD
DNC
AVSS
BINP, BINN
AINN, AINP
VCM
CLKDIV
CLKP, CLKN
NAPSLP
RESETN
OVSS
OVDD
OVDD (PLL)
OVSS (PLL)
SYNCP, SYNCN
LANE0P, LANE0N
LANE1P, LANE1N
LANE2P, LANE2N
SDO
CSB
SCLK
SDIO
-
FUNCTION
1.8V Analog Supply
Do Not Connect
Analog Ground
B-Channel Analog Input Positive, Negative
A-Channel Analog Input Negative, Positive
Common Mode Output
Clock Divider Control
Clock Input True, Complement
Power Control (Nap, Sleep modes)
Power On Reset (Active Low)
Output Ground
1.8V Digital Supply
1.8V Analog Supply for SERDES PLL
Analog Ground Supply for SERDES PLL
JESD204 SYNC Input
SERDES Lane 0
SERDES Lane 1
SERDES Lane 2
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Exposed Paddle. Analog Ground (connect to AVSS)
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISLA222S25IR1Z
ISLA222S25 IR1Z
-40 to +85
48 Ld QFN
L48.7x7G
ISLA222S20IR1Z
ISLA222S20 IR1Z
-40 to +85
48 Ld QFN
L48.7x7G
ISLA222S12IR1Z
ISLA222S12 IR1Z
-40 to +85
48 Ld QFN
L48.7x7G
ISLA224S25IR48EV1Z
FMC Based Evaluation Board (Supports 125/200/250 speed grades), Dual 14-bit Evaluation Board, which can be
configured for 12-bit operation; Interfaces with ADCMB-HSFMCEV1Z Motherboard and Other FPGA Vendor FMC
Based Evaluation Platforms.
ADCMB-HSFMCEV1Z
FMC Based Motherboard
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA222S12, ISLA222S20, ISLA222S25. For more information on MSL
please see techbrief TB363.
Submit Document Feedback
4
FN8302.1
July 6, 2015

4페이지










ISLA222S 전자부품, 판매, 대치품
ISLA222S
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply
across the operating temperature range, -40°C to +85°C. (Continued)
ISLA222S25
ISLA222S20
ISLA222S12
PARAMETER
SYMBOL
MIN MAX MIN MAX MIN MAX
TEST CONDITIONS (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) UNIT
Signal-to-noise and
Distortion (Note 10)
SINAD
fIN = 30MHz
fIN = 105MHz
fIN = 190MHz
fIN = 363MHz
fIN = 495MHz
fIN = 605MHz
Effective Number of Bits
(Note 10)
ENOB
fIN = 30MHz
fIN = 105MHz
fIN = 190MHz
fIN = 363MHz
fIN = 495MHz
fIN = 605MHz
Spurious-free Dynamic
Range (Note 10)
SFDR
fIN = 30MHz
fIN = 105MHz
fIN = 190MHz
fIN = 363MHz
fIN = 495MHz
fIN = 605MHz
Spurious-Free Dynamic
Range Excluding H2, H3
(Note 10)
SFDRX23 fIN = 30MHz
fIN = 105MHz
fIN = 190MHz
fIN = 363MHz
fIN = 495MHz
fIN = 605MHz
Intermodulation
Distortion
IMD fIN = 70MHz
fIN = 170MHz
Channel-to-channel
Isolation
fIN = 10MHz
fIN = 124MHz
Word Error Rate
WER
70.5
69.0 70.4
70.0
69.0
65.4
59.3
11.42
11.17 11.40
11.34
11.16
10.57
9.56
87
74 83
84
79
66
58
87
89
88
84
85
88
-84
-92
88
82
10-13
71.1
70.2 71.0
70.5
68.9
64.0
58.0
11.52
11.37 11.50
11.42
11.16
10.34
9.35
93
76 89
93
88
85
83
93
95
93
88
85
83
-82
-99
90
87
10-13
71.7
70.4 71.3
70.7
67.8
61.4
54.1
11.61
11.40 11.55
11.46
10.97
9.91
8.69
95
76 87
86
71
61
52
98
96
90
85
82
81
-81
-100
100
86
10-13
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
dB
dB
Full Power Bandwidth
FPBW
675 675 675 MHz
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. PSRR is calculated by the equation 20*log10(A/B), where B is the amplitude of a disturber sinusoid on AVDD at the device pins, and A is the amplitude
of the spur in the captured data at the frequency of the disturber sinusoid.
8. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to “Power-on Calibration” on
page 15 and “User Initiated Reset” on page 16 for more detail.
9. The DLL Range setting must be changed via SPI for ADC core sample rates below 80MSPS. The JESD204 transmitter can support ADC sample rates
below 100MSPS, as long as the SERDES lane data rate is greater than or equal to 1Gbps.
10. Minimum specification guaranteed when calibrated at +85°C.
Submit Document Feedback
7
FN8302.1
July 6, 2015

7페이지


구       성 총 30 페이지수
다운로드[ ISLA222S.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
ISLA222P

250MSPS/200MSPS/130MSPS ADC

Intersil
Intersil
ISLA222S

High Speed Serial Output ADC

Intersil
Intersil

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵