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AK9231 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AK9231
기능 Dual 12-Bit 1MSPS SAR A/D Converter
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AK9231 데이터시트, 핀배열, 회로
[AK9231]
AK9231
Dual 12-Bit 1MSPS SAR A/D Converter
1. General Description
The AK9231 is a 12-bit, 1MSPD, SAR A/D converter. It is housed in a space saving ultra-small package
(16-pin QFN).
2. Features
Simultaneous Sampling 12-bit SAR A/D Converter
Sampling Rate: 1MSPS
Unipolar Input Range: 0 ~ VDD
S/(N+D): 71.25dB(Typ.) at 100kHz Input
INL: ±1.25 SB (Max.)
DNL: ±1.0 LSB(Max.)
Power Consumption: IDD=50mW (fs=1MSPS, VDD= 5V)
Power Supply: VDD=2.35 ~ 5.25V
Operational Temperature Range: Ta=-40 ~ 105ºC
Package: Ultra-small 16-pin QFN (3mm x 3mm) Package
VDD
AIN0
AIN1
SAR
S/H Serial I/F
ADC
&
Control
Logic
SAR
S/H
ADC
VSS TEST0
TEST1
Figure 1. AK9231 Block Diagram
SCLK
SDO0
SDO1
CSN
TEST2
TEST3
014010771-E-00
-1-
2014/12




AK9231 pdf, 반도체, 판매, 대치품
[AK9231]
4.2. Pin Functions
Pin No.
1
2
Pin Name
TEST0
TEST1
I/O Function
I
TEST0 (Internal pull down: 50kΩ. Typ.)
This pin must be connected to VSS.
I
TEST1 (Internal pull down: 50kΩ. Typ.)
This pin must be connected to VSS.
3
VDD
- Power Supply: 2.35 ~ 5.25V
4 VSS - Ground
5
SDO0
O Serial Data Output 0
6
SDO1
O Serial Data Output 1
7
CSN
I Chip Select
8
SCK
I Serial Clock Input
9
NC
-
No Connection.
No internal bonding. This pin must be connected to VSS
10
NC
-
No Connection.
No internal bonding. This pin must be connected to VSS
11
TEST2
I
TEST2 (Internal pull down: 50k. Typ.)
This pin must be connected to VSS.
12
TEST3
I
TEST3 (Internal pull down: 50k. Typ.)
This pin must be connected to VSS.
13
AIN1
I ADC1 Input
14
NC
-
No Connection.
No internal bonding. This pin must be connected to VSS
15
NC
-
No Connection.
No internal bonding. This pin must be connected to VSS
16
AIN0
I ADC0 Input
Note:
* 1. Digital input pins (CSN, SCK, TEST0, TEST1, TEST2, TEST3) must not be allowed to float.
4.3. Handling of Unused Pin
Unused I/O pins must be connected appropriately.
Classification Pin Name
Setting
Analog
AIN0, AIN1
VSS
014010771-E-00
-4-
2014/12

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AK9231 전자부품, 판매, 대치품
[AK9231]
8. DC Characteristics
(Ta= -40 ~ 105ºC)
Parameter
Symbol
Min.
Max.
Unit
High-Level Input Voltage
VDD= 2.35 ~ 3.6V
VDD= 4.75 ~ 5.25V
VIH1
VIH2
1.8
2.4
-
-
V
V
Low-Level Input Voltage
VDD= 5V
VDD= 3V
VIL1
-
0.8
V
VIL2
-
0.4
V
High-Level Output Voltage (Iout = -200µA)
VOH VDD-0.2
-
V
Low-Level Output Voltage (Iout = 200µA)
VOL
-
0.4
V
Load Capacitance
CL 30 pF
Input Leakage Current
(* 3) Iin - ±1 µA
Note:
* 3. Except TEST0, TEST1, TEST2 and TEST3 pins. These pins are internally pulled-down. (Typ.50k)
9. Switching Characteristics
(Ta= -40 ~ 105ºC)
Parameter
Symbol Min.
SCK Clock Frequency
fSCK
SCK High Pulse Width
(* 4) tSCKH 0.4 x tSCK
SCK Low Pulse Width
(* 4) tSCKL 0.4 x tSCK
Minimum time from bus 3-state to start of next conversion
CSN “↓” to First SCK “↓”
CSN “↓” to DOUT 0Delay
SCK “↓” to DOUT Valid Delay
tq
tCSS
tCSD
tDCD
40
10
-
-
SCK “↓” to DOUT Valid
VDD= 3V
tDCH1
7
Hold time
VDD= 5V
tDCH2
5.5
Minimum CS pulse
tCS 25
16th SCK“↓” to SDO Hi-Z State
VDD= 3V
VDD= 5V
tCCZ1
tCCZ2
-
-
Note:
* 4. tSCK = 1/ fSCK
Typ.
Max.
20
-
-
-
25
30
-
-
30
20
Unit
MHz
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
9.1. Timing Diagram
CSN
SCK
1/ throughput
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
tCS
SDO
D11
0
D0 Hi-Z
tq
Figure 2. Data Output Timing 1
014010771-E-00
-7-
2014/12

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