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PDF APW7212 Data sheet ( Hoja de datos )
| Número de pieza | APW7212 | |
| Descripción | Step-Up Converter | |
| Fabricantes | ANPEC | |
| Logotipo |  |
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APW7212
1MHz, High-Efficiency, Step-Up Converter with Load Disconnection
Features
General Description
•
Wide 0.8V to V Input Voltage Range
OUT
• Low 1.05V (typical) Start-Up Voltage
• Low 40µA No Load Bias Current
• 100mA Output from a Single AA Cell Input
• 250mA Output from a Dual AA Cell Input
• Internal Synchronous Rectifier
• Up to 92% Efficiency
• <1µA Quiescent Current during Shutdown
• Current-Mode Operation with Internal Compen-
sation
- Stable with Ceramic Output Capacitors
- Fast Line Transient Response
• Fixed 1MHz Oscillator Frequency
• 1.2A Current-Limit Protection
• Built-In Soft-Start
• Over-Temperature Protection with Hysteresis
• Available in a 2mmx2mm TDFN2x2-8 and TSOT-
23-6A Packages
• Halogen and Lead Free Available
(RoHS Compliant)
Applications
• Cell Phone and Smart Phone
• PDA, PMP, and MP3
• Digital Camera
• Boost Regulator
The APW7212 is a synchronous rectifier, fixed switching
frequency (1MHz typical), and current-mode step-up
regulator. The device allows use of small inductors and
output capacitors for portable devices. The current-mode
control scheme provides fast transient response and
good output voltage accuracy.
At light loads, the APW7212 will automatically enter in
pulse frequency modulation(PFM) operation to reduce
the dominant switching losses. During PFM operation,
the IC consumes very low quiescent current and main-
tains high efficiency over the complete load range. The
device has a 1.05V start-up voltage and can operate with
input voltage down to 0.8V after start-up.
The APW7212 also includes current-limit and over-tem-
perature shutdown to prevent damage in the event of an
output overload.
The APW7212 is available in 2mmx2mm TDFN2x2-8 and
TSOT-23-6A packages.
Simplified Application Circuit
L1 8 SW VOUT 2
VIN
0.8V to VOUT
4.7µH
C1
4.7µF
PWM
PFM/
PWM
1 VIN
FB 4
APW7212
3 EN
5 PS
GND 6
GND 7
R1
R2
VOUT
C2
22µF
Pin Configuration
VIN 1
VOUT 2
EN 3
FB 4
8 SW
7 GND
6 GND
5 PS
TDFN2x2-8
(Top View)
SW 1
GND 2
FB 3
6 VIN
5 VOUT
4 EN
TSOT-23-6A
(Top View)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Apr., 2012
1
www.anpec.com.tw
1 page  
APW7212
Typical Operating Characteristics
(Refer to the application circuit in the section"Typical Application Circuits", VIN=1.5V, VOUT=3.3V, TA=25oC unless
otherwise specified )
100
90
80
70
60 VIN=2.4V
50
40
.
30
20 VIN=1.2V
10 VIN=0.9V
0
VIN=1.8V
µ
µ
0.1 1
10 100 1000
100
90
80
70
60
50
40
30
20
10
0
0.1
VIN=1.8V
VIN=2.4V
VIN=1.2V
µ
µ
1 10 100 1000
100
90
80
70
60
50
40
30
20
10 VIN=1.2V
0
0.1
1
VIN=3.6V
VIN=2.4V
VIN=1.8V
µ
µ
10 100 1000
400
350
300
250
200
150
100
50
µ
µ
0
0 0.5 1 1.5 2 2.5 3 3.5
300
250
200
150
100
50 µ
µ
0
0 0.5 1 1.5 2 2.5 3 3.5
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
5
www.anpec.com.tw
5 Page 
APW7212
Application Information (Cont.)
Output Capacitor Selection (Cont.)
Where IPEAK is the peak inductor current. For ceramic ca-
pacitor application, the output voltage ripple is dominated
by the ∆VCOUT. When choosing the input and output ce-
ramic capacitors, the X5R or X7R with their good tem-
perature and voltage characteristics are recommended.
Output Voltage Setting
A resistive divider sets the output voltage. The external
resistive divider is connected to the output, allowing re-
mote voltage sensing as shown in “Typical Application
Circuits”. A suggestion of the maximum value of R1 is
2MΩ and R2 is 600kΩ to keep the minimum current that
provides enough noise rejection ability through the re-
sistor divider. The output voltage can be calculated as
below:
VOUT
=
VREF
⋅ 1+
R1
R2
= 1.231+
R1
R2
Layout Consideration
For all switching power supplies, the layout is an impor-
tant step in the design, especially at high peak currents
and switching frequencies. If the layout is not done
carefully, the regulator may show noise problems and
duty cycle jitter.
1. Since the VOUT supplies IC bias voltage, the output
capacitor should be placed close to the VOUT and
GND. Connecting the capacitor with VOUT and GND
pins by short and wide tracks without using any via
holes for good filtering and minimizing the voltage
ripple.
2. To minimize copper trace connections that can inject
noise into the system, the inductor should be placed
as close as possible to the SW pin to minimize the
noise coupling into other circuits.
3. Since the feedback pin and network is a high imped-
ance circuit the feedback network should be routed
away from the inductor. The feedback pin and feed-
back network should be shielded with a ground plane
or trace to minimize noise coupling into this circuit.
4. A star ground connection or ground plane minimizes
ground shifts and noise is recommended.
Layout Consideration
Via to VIN
C2
VIN
C1
1
VOUT 2
3
4
8 SW
7 GND
6 GND
5
PS
PWM
PFM/PWM
R2
APW7212 Layout Suggestion
VIN
C1
GND
SW
Via To VIN
FB GND VEN
R1 C2 VOUT
Via To VOUT
APW7212 Layout Suggestion
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Apr., 2014
11
www.anpec.com.tw
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet APW7212.PDF ] | |
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