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CH7304 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 CH7304
기능 Single LVDS Transmitter
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CH7304 데이터시트, 핀배열, 회로
Chrontel
CH7304
CH7304 Single LVDS Transmitter
Features
• Single LVDS transmitter
• Supports pixel rate up to 100M pixels/sec
• Supports up to SXGA resolution (1280 x 1024)
• LVDS low jitter PLL
• LVDS 18-bit output
• 2D dither engine
• Panel protection and power down sequencing
• Programmable power management
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Variable voltage interface to graphics device
• Offered in a 64-pin LQFP package
General Description
The CH7304 is a Display Controller device, which accepts
a graphics data stream over one 12-bit wide variable
voltage (1.1V to 3.3V) port. The data stream outputs
through an LVDS transmitter to an LCD panel. A
maximum of 100M pixels per second can be output
through a single LVDS link.
The LVDS transmitter includes a programmable dither
function for support of 18-bit panels. Data is encoded into
commonly used formats, including those detailed in the
OpenLDI and the SPWG specification. Serialized data
output on four differential channels.
XCLK,XCLK*
2
H,V, DE
3
D[11:0]
12
VREF
Clock,
Data,
Sync
Latch &
Demux
Color
Space
Conversion
LVDS PLL
Dither
Engine
LVDS
Encode /
Serialize
Serial Port Control and Misc. Functions
LVDS
Transmit
LDC[3:0],LDC*[3:0]
6 LLC,LLC*
2
2
ENAVDD, ENABKL
XTAL
2 XI/FIN,XO
Figure 1: Functional Block Diagram
201-0000-053 Rev. 1.31, 6/14/2006
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CH7304 pdf, 반도체, 판매, 대치품
CHRONTEL
CH7304
1.2 Pin Description
Table 1: Pin Description
Pin #
1
# of Pins Type
1 Out
2 1 Out
3,4,6,7,9,10, 10
12,13,15,16
-
Symbol
ENABLK
ENAVDD
NC
Description
Back Light Enable
Enable Back-Light of LCD Panel. Output is driven from 0 to DVDD.
Panel Power Enable
Enable panel VDD. Output is driven from 0 to DVDD.
No Connect
20, 21
17,23,26,29
18,24,27,30
32
2
4
4
1
33 1
34 1
37 1
39 1
40 1
41 1
43 1
44 1
45 1
46 1
47 1
Out
Out
Out
In
Out
In
Analog
In/Out
In
In/Out
In
In
In
In
In
LLC, LLC*
LDC[3:0]
LDC[3:0]*
VSWING
XO
XI
LPLL_CAP
CONFIG
SPC
SPD
V
H
VREF
DE
RESET*
LVDS Differential Clock
Positive LVDS differential data[3:0]
Negative LVDS differential data [3:0]
LVDS Voltage Swing Control
This pin sets the swing level of the LVDS outputs. A 2.4K Ohm resistor
should be connected between this pin and LGND (pin 31) using short and
wide traces.
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached
between this pin and XI. However, if an external CMOS clock is attached
to XI, XO should be left open.
Crystal Input / External Reference Input
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached
between this pin and XO. However, an external CMOS compatible clock
can drive the XI input.
LVDS PLL Capacitor
This pin allows coupling of any signal to the on-chip loop filter capacitor.
Configure / Output
This pin configures the device ID.
Serial Port Clock Input
This pin functions as the clock input of the serial port and can operate with
inputs from 1.1V ~ 3.3V. The serial port address of the CH7304 is 75h. For
more details on CH7304 serial port read/write operations, please refer to
AN61.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and can
operate with inputs from 1.1V ~ 3.3V. Outputs are driven from 0 to VDDV.
The serial port address of the CH7304 is 75h. For more details on CH7304
serial port read/write operations, please refer to AN61.
Vertical Sync Input
This pin accepts a vertical sync input for use with the input data. The
amplitude will be 0 to VDDV. VREF signal is the threshold level.
Horizontal Sync Input
This pin accepts a horizontal sync input for use with the input data. The
amplitude will be 0 to VDDV. VREF is the threshold level for this input.
Reference Voltage Input
The VREF pin inputs a reference voltage of VDDV / 2. The signal is
derived externally through a resistor divider and decoupling capacitor, and
will be used as a reference level for data, sync and clock inputs.
Data Enable
This pin accepts a data enable signal which is high when active video data
is input to the device, and remains low during all other times. The levels
are 0 to VDDV. VREF is the threshold level.
Reset * Input (Internal Pull-up)
When this pin is low, the device is held in the power on reset condition.
When this pin is high, reset is controlled through the serial port.
4 201-0000-053 Rev. 1.31, 6/14/2006

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CH7304 전자부품, 판매, 대치품
CHRONTEL
CH7304
2.1.4 Data De-skew Feature
The de-skew feature allows adjustment of the input setup and hold time. The input data D[11:0] can be latched slightly
before or after the latching edge of XCLK depending on the amount of the de-skew. Note that the XCLK is not changed,
only the time at which the data is latched relative to XCLK. The de-skew is controlled using the XCMD[3:0] bits located
in Register 1Dh. The delay tCD between clock and data is given by the following formula:
tCD = - XCMD[3:0] * tSTEP for 0 XCMD[3:0] 7
tCD = (XCMD[3:0] – 8) * tSTEP for 8 XCMD[3:0] 15
where XCMD is a number between 0 and 15 represented as a binary code
tSTEP is the adjustment increment (see Section 4.5)
The delay is also tabulated in Table 8.
2.1.5 Input Data Formats
The CH7304 supports 5 different multiplexed data formats, each of which can be used with a 1X clock latching data on
both clock edges, or a 2X clock latching data with a single edge (rising or falling depending on the value of the MCP bit
– rising refers to a rising edge on the XCLK signal, a falling edge on the XCLK* signal). Received data is formatted and
sent through an internal data bus P[23:0] to the LVDS data path. The input data formats are (IDF[2:0] = 0, 1, 2, 3 and 4):
IDF Description
0 RGB 8-8-8 (2x12-bit)
1 RGB 8-8-8 (2x12-bit) or RGB 5-6-5 (2x8-bit)
2 RGB 5-6-5 (2x8bit)
3 RGB 5-5-5 (2x8-bit)
4 YCrCb 8-8 (2x8-bit) (refer to Register 31h, bit 0)
The input data format is shown in Figure 4. The Pixel Data bus represents a 12-bit or 8-bit multiplexed data stream,
which contains either RGB or YCrCb formatted data. The input data rate is 2X the pixel rate, and each pair of Pn values
(e.g.; P0a and P0b) will contain a complete pixel encoded as shown in Table 2 through Table 4.
For multiplexed input data formats, data can be latched from the graphics controller by either rising only or falling only
clock edges, or by both rising and falling clock edges. The MCP bit selects the rising or the falling clock edge, where
rising refers to rising edge on the XCLK signals and falling edge on the XCLK*. It is assumed that the first clock cycle
following the leading edge of the incoming horizontal sync signal contains the first word (Pxa) of a pixel, if an active
pixel was present immediately following the horizontal sync. This does not mean that active data should immediately
follow the horizontal sync, however. When the input is a YCrCb data stream the color-difference data will be
transmitted at half the data rate of the luminance data, with the sequence being set as Cb, Y, Cr, Y, where Cb0,Y0,Cr0
refers to co-sited luminance and color-difference samples and the following Y1 byte refers to the next luminance sample,
per ITU-R BT.656 standards (the clock frequency is dependent upon the current mode, and is not 27MHz as specified in
ITU-R BT.656). All non-active pixels should be 0 in RGB formats, and 16 for Y, 128 for Cr and Cb in YCrCb formats.
H
XCLK
(2X)
XCLK
(1X)
DE
D[11:0]
P0a P0b P1a P1b P2a P2b
Figure 4: 12-bit Multiplexed Input Data Formats (IDF = 0,1,2,3, 4)
201-0000-053 Rev. 1.31, 6/14/2006
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