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CHPHT2010 데이터시트 PDF




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기능 Thick Film Chip Resistor
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CHPHT2010 데이터시트, 핀배열, 회로
www.vishay.com
CHPHT
Vishay Sfernice
High Temperature (245 °C) Thick Film Chip Resistor
For applications such as down hole applications or aircraft
breaking systems, the need for parts able to withstand very
severe conditions (temperature as high as 230 °C powered
or up to 245 °C un-powered) has leaded Vishay Sfernice to
push out the limit of the thick film technology. Designers
might read the application note “Power Dissipation
Considerations in High Precision Vishay Sfernice Thin Film
Chips Resistors and Arrays (P, PRA etc.) (High Temperature
Applications)” (www.vishay.com/doc?53047) in conjunction
with this data sheet to help them to properly design their
PCBs and get the best performances of the CHPHT.
Vishay Sfernice R&D engineers will be willing to support any
customer design considerations.
DIMENSIONS in millimeters
FEATURES
• High temperature (245 °C)
• Large ohmic value range 0.1 to 100 M
• Operating temperature range
(-55 °C to +230 °C)
Available
• SMD wraparound chip resistor
• Storage temperature range
(-55 °C to +245 °C)
• Gold terminations for HMP process (< 1 μm thick) for
temperature up to 245 °C
• Tin/silver terminations for operating temperature up to
200 °C
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
DC
E
A
CASE SIZE
0603
0805
1206
2010
A
± 0.152
1.60
1.85
3.00
5.03
B
± 0.127
0.90
1.25
1.73
2.64
SUGGESTED LAND PATTERN (to IPC-7351A)
CASE SIZE
0603
0805
1206
2010
Zmax.
2.15
2.70
3.85
5.88
Gmin.
Zmax.
B
C
± 0.127
0.38
0.38
0.38
0.50
Gmin.
0.39
0.44
1.59
3.62
D
± 0.127
0.31
0.31
0.40
0.50
Xmax.
E
± 0.127
0.40
0.50
0.50
0.50
Xmax.
1.03
1.38
1.85
2.77
Revision: 21-Jul-14
1 Document Number: 52032
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000




CHPHT2010 pdf, 반도체, 판매, 대치품
www.vishay.com
PERFORMANCE
TESTS
Termination adhesion
Resistance to solder heat
Rapid temperature change
Climatic sequence
Humidity (steady state)
Moisture resistance
Short time overload
Load life
Shelf life
CONDITIONS
5N for 10 s
Immersion 10 s
in Sn/Pb 60/40
at +260 °C
5 cycles
-55 °C to +155 °C
Phase A dry heat
Phase B damp heat
Phase C cold -55 °C
Phase D damp heat 5 cycles
56 days
AEC-Q200
85 °C/85 % RH/Pn
1000 h
6.25 Pn
for 2 s
1000 h at rated power
at 230 °C
1000 h at 245 °C
REQUIREMENTS
± (0.25 % + 0.05 )
± (0.25 % + 0.05 )
± (0.25 % + 0.05 )
± (1 % + 0.05 )
± (1 % + 0.05 )
3 % + 0.05
± (0.25 % + 0.05 )
-
-
CHPHT
Vishay Sfernice
TYPICAL VALUES
AND DRIFTS
< ± 0.1 %
< ± 0.1 %
< ± 0.1 %
< ± 0.2 %
< ± 0.2 %
Max. < 3 % + 0.05
< ± 0.1 %
1 % max.
1 % max.
GLOBAL PART NUMBER INFORMATION
Global Part Numbering: CHPHT0805K1001FGT
C H P H T 0 8 0 5 K 10 0 1FGT
GLOBAL
MODEL
CHPHT
SIZE
0603
0805
1206
2010
TCR
VALUE
TOLERANCE
TERMINATION (1)
PACKAGING
OPTION
K = 100 ppm
L = 200 ppm
The first 3 digits
are significant
figures and the
last digit specifies
the number of
zeros to follow.
R designates
decimal point
F=±1%
G=±2%
J=±5%
N: SnAg over nickel barrier
G: Gold over nickel barrier
For more
information see
“Codification of
packaging”
table
Leave blank
if no option
10R0 = 10
3901 = 3900
1004 = 1 M
Note
(1) N terminations for temperature up to 200 °C
G terminations for temperature up to 230 °C
Revision: 21-Jul-14
4 Document Number: 52032
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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CHPHT2010

Thick Film Chip Resistor

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