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PDF 5P49V5901 Data sheet ( Hoja de datos )
| Número de pieza | 5P49V5901 | |
| Descripción | Programmable Clock Generator | |
| Fabricantes | Integrated Device Technology | |
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Programmable Clock Generator
5P49V5901
DATASHEET
Description
Features
The 5P49V5901 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single reference clock.
The reference clock can come from one of the two redundant
clock inputs. A glitchless manual switchover function allows
one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
XOUT
XIN/REF
VDDA
CLKSEL
1 24 23
22
21
20
19
18
2 17
3 16
4
EPAD
15
5 14
6 13
7 8 9 10 11 12
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
24-pin VFQFPN
• Generates up to four independent output frequencies
• High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
• Four fractional output dividers (FODs)
• Independent Spread Spectrum capability on each output
pair
• Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
• I2C serial programming interface
• One reference LVCMOS output clock
• Four universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
• I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
• Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
– Crystal frequency range: 8MHz to 40MHz
• Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
1MHz to 350MHz
• Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
• Redundant clock inputs with manual switchover
• Programmable loop bandwidth
• Programmable output to output skew
• Programmable slew rate control
• Programmable crystal load capacitance
• Individual output enable/disable
• Power-down mode
• 1.8V, 2.5V or 3.3V core VDDD, VDDA
• Available in 24-pin VFQFPN 4mm x 4mm package
• -40° to +85°C industrial temperature operation
5P49V5901 NOVEMBER 11, 2016
1 ©2016 Integrated Device Technology, Inc.
1 page  
PLL Features and Descriptions
Spread Spectrum
To help reduce electromagnetic interference (EMI), the
5P49V5901 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread energy
across a broader range of frequencies, lowering system EMI.
The 5P49V5901 implements spread spectrum using the
Fractional-N output divide, to achieve controllable modulation
rate and spreading magnitude. The Spread spectrum can be
applied to any output clock, any clock frequency, and any
spread amount from ±0.25% to ±2.5% center spread and
-0.5% to -5% down spread.
Table 2: Loop Filter
PLL loop bandwidth range depends on the input reference
frequency (Fref) and can be set between the loop bandwidth
range as shown in the table below.
Input Reference
Loop
Loop
Frequency–Fref Bandwidth Min Bandwidth Max
(MHz)
(kHz)
(kHz)
1 40 126
350 300 1000
5P49V5901 DATASHEET
If OUT0_SEL_I2CB was 0 at POR, alternate configurations
can only be loaded via the I2C interface.
Table 4: Input Clock Select
Input clock select. Selects the active input reference source in
manual switchover mode.
0 = XIN/REF, XOUT (default)
1 = CLKIN, CLKINB
CLKSEL Polarity can be changed by I2C programming as
shown in the table below.
PRIMSRC
0
0
1
1
CLKSEL
0
1
0
1
Source
XIN/REF
CLKIN, CLKINB
CLKIN, CLKINB
XIN/REF
PRIMSRC is bit 1 of Register 0x13.
Table 3: Configuration Table
This table shows the SEL1, SEL0 settings to select the
configuration stored in OTP. Four configurations can be stored
in OTP. These can be factory programmed or user
programmed.
OUT0_SEL_I2CB SEL1 SEL0 I2C REG0:7 Config
@ POR
Access
1
00
No
0
0
1
01
No
0
1
1
10
No
0
2
1
11
No
0
3
0
XX
Yes
1 I2C
defaults
0
XX
Yes
0
0
At power up time, the SEL0 and SEL1 pins must be tied to
either the VDDD/VDDA power supply so that they ramp with
that supply or are tied low (this is the same as floating the
pins). This will cause the register configuration to be loaded
that is selected according to Table 3 above. Providing that
OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after
the first 10mS of operation the levels of the SELx pins can be
changed, either to low or to the same level as VDDD/VDDA.
The SELx pins must be driven with a digital signal of < 300nS
Rise/Fall time and only a single pin can be changed at a time.
After a pin level change, the device must not be interrupted for
at least 1ms so that the new values have time to load and take
effect.
NOVEMBER 11, 2016
5
PROGRAMMABLE CLOCK GENERATOR
5 Page 
5P49V5901 DATASHEET
Table 6: I2C Bus DC Characteristics
Symbol
VIH
VIL
VHYS
IIN
VOL
Parameter
Input HIGH Level
Input LOW Level
Hysteresis of Inputs
Input Leakage Current
Output LOW Voltage
Conditions
Min
For SEL1/SDA pin and SEL0/SCL pin 0.7xVDDD
For SEL1/SDA pin and SEL0/SCL pin GND-0.3
0.05xVDDD
-1
IOL = 3 mA
Typ Max Unit
5.5 2
V
0.3xVDDD V
V
30 µA
0.4 V
Table 7: I2C Bus AC Characteristics
Symbol
Parameter
FSCLK Serial Clock Frequency (SCL)
tBUF Bus free time between STOP and START
tSU:START Setup Time, START
tHD:START Hold Time, START
tSU:DATA Setup Time, data input (SDA)
tHD:DATA Hold Time, data input (SDA) 1
tOVD Output data valid from clock
CB Capacitive Load for Each Bus Line
tR Rise Time, data and clock (SDA, SCL)
tF Fall Time, data and clock (SDA, SCL)
tHIGH HIGH Time, clock (SCL)
tLOW LOW Time, clock (SCL)
tSU:STOP Setup Time, STOP
Min Typ
10
1.3
0.6
0.6
0.1
0
20 + 0.1xCB
20 + 0.1xCB
0.6
1.3
0.6
Max
400
0.9
400
300
300
Unit
kHz
µs
µs
µs
µs
µs
µs
pF
ns
ns
µs
µs
µs
Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
Note 2: I2C inputs are 5V tolerant.
NOVEMBER 11, 2016
11 PROGRAMMABLE CLOCK GENERATOR
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 5P49V5901.PDF ] | |
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